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Layer Router for Grayscale Stego - A Hardware Architecture on FPGA and ASIC Platforms
SASTRA University, India.
SASTRA University, India.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
SASTRA University, India.
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2014 (English)In: Journal of Scientific and Industrial Research, ISSN 0022-4456, E-ISSN 0975-1084, Vol. 73, no 11, 701-703 p.Article in journal (Refereed) Published
Abstract [en]

In the present era of secret communication, steganography has obtained a significant place in information security by means of offering variety of techniques for cleverly hiding the information. In addition to the existing hardware stego algorithms, an adaptive block hardware stego system has been proposed in this paper which follows a shortest path algorithm for performing secret concealment in grayscale images. The proposed image steganographic hardware architecture which adopts traversal procedures predominant in area routing has been implemented bath in Stratix III FPGA as well as ASIC Platforms.

Place, publisher, year, edition, pages
NATL INST SCIENCE COMMUNICATION-NISCAIR , 2014. Vol. 73, no 11, 701-703 p.
Keyword [en]
Hardware Steganography; FPGA; ASIC; Information security
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-112823ISI: 000344838700001OAI: oai:DiVA.org:liu-112823DiVA: diva2:776852
Note

Funding Agencies|DRDO, New Delhi [ERIP/ER/1003836/M/01/1230]

Available from: 2015-01-08 Created: 2014-12-17 Last updated: 2017-12-05

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