Synthesis of time-to-digital converters
(English)Manuscript (preprint) (Other academic)
We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-113277OAI: oai:DiVA.org:liu-113277DiVA: diva2:780436