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Circuit Design for All-Digital Frequency Synthesizers
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The market for low cost portable electronics is rapidly growing. Physical activity monitors, portable music players, and smart watches are fast becoming a part of daily life. As the market for wearable devices has grown, a primary concern for IC manufacturers is to provide low cost, low power and lightweight circuit solutions. In a bid to lower the costs and extend battery life there is an increased interest in using low-cost, low-power CMOS processes. As a result fully integrated systems on chips (SOC) have been realized that efficiently perform the required functions. These SOCs house digital, analog and in some cases radio circuits on a single die in a bid to reduce cost and improve productivity.

Phase Locked Loops (PLLs) are a key building block for all SOCs where they are used to generate clock signals for synchronous systems. In monolithic implementations the design cost of a circuit is measured in terms of the silicon area and not the number of devices in the circuit. With the advent of all-digital techniques, there is a renewed interest in the design of compact PLLs as the area occupied by the traditional PLLs is very large due to the presence of large passive components in the loop filter and the oscillator. As a result, various digital circuit design techniques are being explored to design compact all-digital PLLs (ADPLLs) while satisfying the performance requirements for the target applications.

The focus of this work is to explore new techniques for area, power and time efficient design of ADPLL component blocks. The first part of this works focuses on the feasibility of using automatic place and route (P&R) tools to synthesize a time-to-digital converter (TDC). An area efficient TDC is synthesized in a 65 nm CMOS process using automated P&R which exhibits a time resolution of 6.5 ps with an input sampling rate of 100 MS/s while occupying an area of 0.002 mm2. A modified switching scheme is also presented which reduces the power consumption of the thermometer-to-binary encoder by up to 40%.

The second part of this thesis proposes a power supply filter for mitigating the affect of cyclostationary noise on the voltage controlled ring oscillator. The key idea is to raise the impedance in the current supply during the sensitive periods and lower it during insensitive periods of the oscillator operation. To demonstrate the feasibility of the proposed filter, a pseudo differential ring oscillator is designed in a 65 nm CMOS process which exhibits an rms jitter of less than 14 ps at 2.4 GHz in the presence of a 500 mV noise tone in the power supply.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. , 37 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1701
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-113281ISBN: 978-91-7519-144-7 (print)OAI: oai:DiVA.org:liu-113281DiVA: diva2:780494
Presentation
2015-01-30, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-14Bibliographically approved
List of papers
1. Synthesis of time-to-digital converters
Open this publication in new window or tab >>Synthesis of time-to-digital converters
(English)Manuscript (preprint) (Other academic)
Abstract [en]

We investigate the synthesis of Vernier delay-line time-to-digital converters (TDCs). A modular approach using a TDC architecture based on multiplexers is proposed. The required circuit components are ordinarystandard cells readily available in most CMOS technologies, which renders the TDC suitable for inter-process portability. To demonstrate the viability of the proposed approach a TDC is synthesized to match the specifications of a custom designed reference TDC, reducing the time for layout from 6 weeks to 2 hours. Both TDCs are designed in a 65 nm CMOS technology and achieve a time resolution in the order of 6 ps and a power consumption of 1.3 mW at a sample rate of 100 MS/s.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113277 (URN)
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-14
2. A modified switching scheme for multiplexer based thermometer-to-binary encoders
Open this publication in new window or tab >>A modified switching scheme for multiplexer based thermometer-to-binary encoders
2014 (English)In: 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, 1-4 p.Conference paper, Oral presentation only (Refereed)
Abstract [en]

A modified switching scheme for thermometer-to-binary encoders used in time-to-digital converters (TDCs) is presented. The proposed scheme enables power savings up to 40% for a 256 bit encoder by taking advantage of the operating nature of the TDCs and by preventing unnecessary switchings to pass through the encoder tree. The efficiency of the proposed scheme is verified for thermometer encoders of different word lengths. It is observed that the power savings increase with the length of the thermometer encoder.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113278 (URN)10.1109/NORCHIP.2014.7004733 (DOI)978-1-4799-5442-1 (ISBN)
Conference
NORCHIP 2014. The Nordic Microelectronics event, 32nd Norchip Conference 27-28 October 2014, Tampere, Finland
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-03-26Bibliographically approved
3. Frequency control schemes for single ended ring oscillators
Open this publication in new window or tab >>Frequency control schemes for single ended ring oscillators
2011 (English)In: 20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden, IEEE , 2011, 361-364 p.Conference paper, Oral presentation only (Refereed)
Abstract [en]

An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.

Place, publisher, year, edition, pages
IEEE, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113279 (URN)10.1109/ECCTD.2011.6043361 (DOI)978-1-4577-0616-5 (ISBN)978-1-4577-0617-2 (ISBN)
Conference
20th European Conference on Circuit Theory and Design (ECCTD), 2011, August 29-31, Linköping, Sweden
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-21Bibliographically approved
4. A novel technique to reduce the supply sensitivity of CMOS ring oscillators
Open this publication in new window or tab >>A novel technique to reduce the supply sensitivity of CMOS ring oscillators
2014 (English)Manuscript (preprint) (Other academic)
Abstract [en]

A technique to abbreviate the supply sensitivity of CMOS ring oscillators is presented. By switching the power source from the noisy power supply to a battery during sensitive zero crossings the noise performance of the ring oscillator is improved. The proposed technique can be used in conjunction with other regulation techniques to enhance the performance of ring oscillators in phase locked loops. The proposed switching circuit using a pseudo differential ring oscillator are designed in a 65 nm CMOS process to demonstrate the viability of the proposed scheme in deep submicron process with reduced voltage headroom. At 2 GHz the outputclock exhibits a jitter of less than 14 ps while subjected to a 500 mV noise tone at 500 MHz.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113280 (URN)
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2015-01-14

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Touqir Pasha, Muhammad

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