Timing challenges in high-speed interleaved ΔΣ DACs
2014 (English)In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, 46-49 p.Conference paper (Refereed)
Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.
Place, publisher, year, edition, pages
IEEE , 2014. 46-49 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-114736DOI: 10.1109/ISICIR.2014.7029513OAI: oai:DiVA.org:liu-114736DiVA: diva2:792224
14th International Symposium on Integrated Circuits (ISIC), 10-12 December, Singapore 2014