Timing and Synchronization over Ethernet
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
In this thesis an investigation will be done on how time and frequency can be synchronized over Ethernet with help of Precision Time Protocol and Synchronous Ethernet. The goal is to achieve a high accuracy in the synchronization when a topology of 10 cascaded nodes is used. Different approaches may be used when implementing Precision Time Protocol for synchronization. They will be investigated and the best approach for a good accuracy will be proposed. Another question that this thesis will cover is how to recover a radio frequency, a multiple of 3.84 MHz from Ethernets 10.3125 GHz.
By using hardware support for the timestamps and transparent clocks in the forwarding nodes the best accuracy is achieved for the time and phase synchronization. Combining this with Synchronous Ethernet for frequency synchronization, to get a traceable clock through the system, will lead to the best result. The total error does not need to be greater than 1.46~ns if the asymmetry in the medium is neglected and a welldesigned PCS and FIFO are used. Recovering the radio frequency from Ethernet is done by using the highest common frequency, either an integer phase locked loop or a fractional phase locked loop can be used. The fractional phase locked loop will give a better result but will contribute with spurs that the integer phase locked loop does not.
Place, publisher, year, edition, pages
2015. , 38 p.
Ethernet, PTP, SyncE, Time & Frequency
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-115882ISRN: LiTH-ISY-EX--15/4824--SEOAI: oai:DiVA.org:liu-115882DiVA: diva2:797013
Subject / course
2015-02-20, Signalen, Linköping, 13:00