An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs
2015 (English)In: 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, Jan. 19-22, 2015., Institute of Electrical and Electronics Engineers (IEEE), 2015, 526-531 p.Conference paper (Refereed)
In a modern 3D IC, electrical connections between vertically stacked dies are made using through silicon vias. Through silicon vias are subject to undesirable early-life effects such as protrusion as well as void formation and growth. These effects result in opens, resistive opens, and stress induced carrier mobility reduction, and consequently circuit failures. Operating the ICs under extreme temperature cycling can effectively accelerate such early-life failures and make them detectable at the manufacturing test process. An integrated temperature-cycling acceleration and test technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration procedures. All these result in a reduction in the overall test costs. The proposed method is a schedule-based solution that creates the required temperature cycling effect along with performing the tests. Experimental results demonstrate its efficiency.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. 526-531 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-116878DOI: 10.1109/ASPDAC.2015.7059060ISI: 000380442800103ISBN: 978-1-4799-7792-5OAI: oai:DiVA.org:liu-116878DiVA: diva2:801209