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Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, 646-650 p.Article in journal (Refereed) Published
Abstract [en]

Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2015. Vol. 62, no 7, 646-650 p.
Keyword [en]
Delta-sigma (Delta Sigma) modulator; digital Delta Sigma modulator; digital-to-analog converter (DAC); duty cycle; finite-impulse-response (FIR) filter; time interleaving
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-120215DOI: 10.1109/TCSII.2015.2415691ISI: 000357126000006OAI: oai:DiVA.org:liu-120215DiVA: diva2:842687
Note

Funding Agencies|Swedish Foundation for Strategic Research

Available from: 2015-07-21 Created: 2015-07-20 Last updated: 2017-12-04
In thesis
1. Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters
Open this publication in new window or tab >>Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ΔΣ DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced.

Achieving a large bandwidth from ΔΣ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ΔΣ DAC architectures, even in nanometer CMOS processes. Time-interleaved ΔΣ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.

The rst work is an 8-GS/s interleaved ΔΣ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype.

The performance of a two-channel interleaved ΔΣ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ΔΣ DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented.

The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ΔΣ DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ΔΣ DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2015. 117 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1688
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer Science Signal Processing
Identifiers
urn:nbn:se:liu:diva-120626 (URN)10.3384/diss.diva-120626 (DOI)978-91-7519-017-4 (ISBN)
Public defence
2015-09-25, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2015-08-19 Created: 2015-08-19 Last updated: 2015-08-19Bibliographically approved

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Bhide, AmeyaOjani, AminAlvandpour, Atila

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