Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, Vol. 62, no 7, 646-650 p.Article in journal (Refereed) Published
Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2015. Vol. 62, no 7, 646-650 p.
Delta-sigma (Delta Sigma) modulator; digital Delta Sigma modulator; digital-to-analog converter (DAC); duty cycle; finite-impulse-response (FIR) filter; time interleaving
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-120215DOI: 10.1109/TCSII.2015.2415691ISI: 000357126000006OAI: oai:DiVA.org:liu-120215DiVA: diva2:842687
Funding Agencies|Swedish Foundation for Strategic Research2015-07-212015-07-202015-08-19