ePUMA: A Processor Architecture for Future DSP
2015 (English)In: International Conference on Digital Signal Processing (DSP), Singapore, 21-24 July, 2015, 2015Conference paper (Refereed)
Since the breakdown of Dennard scaling the primary design goal for processor designs has shifted from increasing performance to increasing performance per Watt. The ePUMA platform is a flexible and configurable DSP platform that tries to address many of the problems with traditional DSP designs, to increase performance, but use less power. We trade the flexibility of traditional VLIW DSP designs for a simpler single instruction issue scheme and instead make sure that each instruction can perform more work. Multi-cycle instructions can operate directly on vectors and matrices in memory and the datapaths implement common DSP subgraphs directly in hardware, for high compute throughput. Memory bottlenecks, that are common in other architectures, are handled with flexible LUT-based multi-bank memory addressing and memory parallelism. A major contributor to energy consumption, data movement, is reduced by using heterogeneous interconnect and clustering compute resources around local memories for simple data sharing. To evaluate ePUMA we have implemented the majority of the kernel library from a commercial VLIW DSP manufacturer for comparison. Our results not only show good performance, but also an order of magnitude increase in energy- and area efficiency. In addition, the kernel code size is reduced by 91% on average compared to the VLIW DSP. These benefits makes ePUMA an attractive solution for future DSP.
Place, publisher, year, edition, pages
IdentifiersURN: urn:nbn:se:liu:diva-120396ISBN: 978-1-4799-8058-1OAI: oai:DiVA.org:liu-120396DiVA: diva2:844264
IEEE International Conference on Digital Signal Processing (DSP)