Implementation of a Driver Circuit in 65nm CMOS technology for Body-Coupled Communication
2014 (English)In: 2014 1ST INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATION and COMMUNICATION TECHNOLOGY (ICEEICT 2014), IEEE , 2014Conference paper (Refereed)
This paper presents a newly cascaded voltage mode tri-state driver circuit for body-coupled communication (BCC) designed in 65 mu CMOS technology. Each stage of the driver circuit has been resized to meet the requirement of the BCC. It has a driving capability of 6 mA from 1.2 V supply with 10 MHz operating frequency. Different analysis has been performed to get the optimum results for the proposed circuit. The analysis shows cycle to cycle jitter to be less than one and power supply rejection ratio (PSRR) 65 dB, indicating the good emission of supply noise. In addition, the driver circuit does not require a filter to emit the noise because the body acts like a low pass filter.
Place, publisher, year, edition, pages
IEEE , 2014.
BCC; driver circuit; noise analysis; corner analysis; PSRR
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-120671ISI: 000358383900082ISBN: 978-1-4799-4819-2OAI: oai:DiVA.org:liu-120671DiVA: diva2:847506
1st International Conference on Electrical Engineering and Information and Communication Technology (ICEEICT)