On-Chip Phase Measurement Design Study in 65nm CMOS Technology
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.
Place, publisher, year, edition, pages
2015. , 92 p.
BIST, Vernier Oscillators, SAFF, Built-in-Jitter-Measurement, Timing Amplifier.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-120912ISRN: LiTH-ISY-EX--15/4856--SEOAI: oai:DiVA.org:liu-120912DiVA: diva2:849645
Subject / course
2015-06-10, Nollstället, LIU University, Linkoping, 22:19 (English)
Dabrowski, Jerzy, Professor