Highly Linear Inductively Degenerated 0.13 mu m CMOS LNA using FDC Technique
2014 (English)In: 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), IEEE , 2014, 225-228 p.Conference paper (Refereed)
In this paper, a highly linear, inductively degenerated, common source narrowband LNA is presented. An extremely simple feed-forward distortion circuit (FDC) which consists of an appropriately sized ac-coupled diode connected NMOS is proposed. This circuit generates distortion components at output, when added at the input node as a feed forward element (M-6). These distortion components partially cancel the 3rd order nonlinearity of the cascode pair (M-2 and M-3), thus improving the overall linearity of LNA. The prototype is manufactured in standard 0.13 mu m CMOS process from IBM. Simulation and partial measurement results show the S11 and S22 to be -19.27dB and -7.14dB respectively at 2.45GHz. The simulation results of the LNA demonstrate a power gain of 18.5dB, NF of 4.38dB, input referred 1dBCP of -11.76dBm and IIP3 of +0.7dBm consuming 27.7mA from 1.0V power supply. The proposed LNA achieves the best input referred IIP3 reported in recent literature using 0.13 mu m CMOS in 2.4GHz frequency band.
Place, publisher, year, edition, pages
IEEE , 2014. 225-228 p.
High linearity; feed forward distortion cancellation (FDC); linear LNA; linearity improvement of LNA; IIP3 of LNA; WLAN LNA
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-122080DOI: 10.1109/APCCAS.2014.7032760ISI: 000361128200054ISBN: 978-1-4799-5230-4OAI: oai:DiVA.org:liu-122080DiVA: diva2:862017
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)