Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
2015 (English)In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, IEEE , 2015, 496-499 p.Conference paper (Refereed)
In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.
Place, publisher, year, edition, pages
IEEE , 2015. 496-499 p.
High resolution; pipeline; power consumption; successive approximation analog-to-digital; converter; two-stage
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-122623DOI: 10.1109/MIXDES.2015.7208570ISI: 000364071600094ISBN: 978-8-3635-7806-0OAI: oai:DiVA.org:liu-122623DiVA: diva2:871704
The22 International Conference “Mixed Design of Integrated Circuits and Systems”(MIXDES), Toruń, Poland, 25-27 June 2015