A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, 743-747 p.Article in journal (Refereed) Epub ahead of print
This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016. Vol. 63, no 8, 743-747 p.
Analog-to-digital converter, ADC, successive approximation register, SAR, ultra-low-voltage
IdentifiersURN: urn:nbn:se:liu:diva-122729DOI: 10.1109/TCSII.2016.2531099ISBN: 978-1-4799-9877-7OAI: oai:DiVA.org:liu-122729DiVA: diva2:872374
At the time for thesis presentation publication was in status: Manuscript2015-11-182015-11-182016-08-04Bibliographically approved