Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
2015 (English)In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE , 2015, 249-252 p.Conference paper (Refereed)
This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.
Place, publisher, year, edition, pages
IEEE , 2015. 249-252 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
CMOS digital integrated circuits;analogue-digital conversion;buffer circuits;digital-analogue conversion;flip-flops;printed circuits;reference circuits;CMOS;DAC;ENOB;FoM;PCB trace;PSRR performance;RVBuffer;SAR ADC;analog-to-digital converter;bondwire;complementary metal oxide semiconductor;digital-to-analog converter;effective number of bits;energy efficiency;figure of merit;near-Nyquist input;parasitic inductance;post-layout simulation;power 697 muW;power supply rejection ratio;reference voltage buffer;sampling frequency;settling-time noise;size 65 nm;successive approximation register;voltage 1.2 V;word length 10 bit;Capacitors;Clocks;Gain;Inductance;Noise;Power demand;System-on-chip
IdentifiersURN: urn:nbn:se:liu:diva-122731DOI: 10.1109/ISCAS.2015.7168617ISI: 000371471000062OAI: oai:DiVA.org:liu-122731DiVA: diva2:872384
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Date 24-27 May, Lisbon, Portugal