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Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2015 (English)In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE , 2015, 249-252 p.Conference paper (Refereed)
Abstract [en]

This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

Place, publisher, year, edition, pages
IEEE , 2015. 249-252 p.
Series
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Keyword [en]
CMOS digital integrated circuits;analogue-digital conversion;buffer circuits;digital-analogue conversion;flip-flops;printed circuits;reference circuits;CMOS;DAC;ENOB;FoM;PCB trace;PSRR performance;RVBuffer;SAR ADC;analog-to-digital converter;bondwire;complementary metal oxide semiconductor;digital-to-analog converter;effective number of bits;energy efficiency;figure of merit;near-Nyquist input;parasitic inductance;post-layout simulation;power 697 muW;power supply rejection ratio;reference voltage buffer;sampling frequency;settling-time noise;size 65 nm;successive approximation register;voltage 1.2 V;word length 10 bit;Capacitors;Clocks;Gain;Inductance;Noise;Power demand;System-on-chip
National Category
Signal Processing
Identifiers
URN: urn:nbn:se:liu:diva-122731DOI: 10.1109/ISCAS.2015.7168617ISI: 000371471000062OAI: oai:DiVA.org:liu-122731DiVA: diva2:872384
Conference
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Date 24-27 May, Lisbon, Portugal
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-04-07
In thesis
1. Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces
Open this publication in new window or tab >>Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.

The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2.

The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2016. 122 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1728
National Category
Signal Processing Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122730 (URN)10.3384/diss.diva-122730 (DOI)978-91-7685-890-5 (print) (ISBN)
Public defence
2016-01-22, Visionen, B-huset, Campus Valla, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2015-12-11Bibliographically approved

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