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Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.

The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2.

The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2016. , 122 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1728
National Category
Signal Processing Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-122730DOI: 10.3384/diss.diva-122730ISBN: 978-91-7685-890-5 (print)OAI: oai:DiVA.org:liu-122730DiVA: diva2:872401
Public defence
2016-01-22, Visionen, B-huset, Campus Valla, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2015-12-11Bibliographically approved
List of papers
1. A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
Open this publication in new window or tab >>A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, 743-747 p.Article in journal (Refereed) Published
Abstract [en]

This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Keyword
Analog-to-digital converter, ADC, successive approximation register, SAR, ultra-low-voltage
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122729 (URN)10.1109/TCSII.2016.2531099 (DOI)000381440000007 ()978-1-4799-9877-7 (ISBN)
Note

At the time for thesis presentation publication was in status: Manuscript

Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2017-12-01Bibliographically approved
2. A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
Open this publication in new window or tab >>A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, 28-38 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

Place, publisher, year, edition, pages
Elsevier, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-111957 (URN)10.1016/j.vlsi.2015.01.002 (DOI)000357054300003 ()
Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2017-12-05Bibliographically approved
3. Design of a Sampling Switch for a 0.4-V SAR ADC Using a Multi-Stage Charge Pump
Open this publication in new window or tab >>Design of a Sampling Switch for a 0.4-V SAR ADC Using a Multi-Stage Charge Pump
2014 (English)In: NORCHIP 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-114725 (URN)10.1109/NORCHIP.2014.7004703 (DOI)
Conference
32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland
Available from: 2015-03-03 Created: 2015-03-03 Last updated: 2015-11-18Bibliographically approved
4. Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
Open this publication in new window or tab >>Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
2015 (English)In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE , 2015, 249-252 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

Place, publisher, year, edition, pages
IEEE, 2015
Series
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Keyword
CMOS digital integrated circuits;analogue-digital conversion;buffer circuits;digital-analogue conversion;flip-flops;printed circuits;reference circuits;CMOS;DAC;ENOB;FoM;PCB trace;PSRR performance;RVBuffer;SAR ADC;analog-to-digital converter;bondwire;complementary metal oxide semiconductor;digital-to-analog converter;effective number of bits;energy efficiency;figure of merit;near-Nyquist input;parasitic inductance;post-layout simulation;power 697 muW;power supply rejection ratio;reference voltage buffer;sampling frequency;settling-time noise;size 65 nm;successive approximation register;voltage 1.2 V;word length 10 bit;Capacitors;Clocks;Gain;Inductance;Noise;Power demand;System-on-chip
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122731 (URN)10.1109/ISCAS.2015.7168617 (DOI)000371471000062 ()
Conference
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Date 24-27 May, Lisbon, Portugal
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-04-07
5. A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
Open this publication in new window or tab >>A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, 13-16 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

Place, publisher, year, edition, pages
IEEE, 2015
Keyword
CMOS integrated circuits;analogue-digital conversion;mixed analogue-digital integrated circuits;operational amplifiers;silicon-on-insulator;PGA;SAR ADC;Si;UTBB FDSOI CMOS process;analog-mixed-signal circuits;continuous-time CMFB circuits;frequency 4.3 MHz;fully-differential OTA;gain 6 dB;gain 70 dB;operational transconductance amplifier;power 2.9 muW;programmable gain amplifier;reverse body bias;size 28 nm;temperature -20 degC to 85 degC;time 5.8 mus;ultrathin box and body fully-depleted silicon-on-insulator;voltage 1 V;word length 9 bit;Electronics packaging;Gain;Linearity;MOS devices;Resistors;Threshold voltage;Transistors
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122727 (URN)10.1109/ECCTD.2015.7300114 (DOI)000380498200096 ()978-1-4799-9877-7 (ISBN)
Conference
2015 European Conference on Circuit Theory and Design (ECCTD), August 24-26, Trondheim, Norway
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-25Bibliographically approved
6. An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias
Open this publication in new window or tab >>An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias
2015 (English)In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-122728 (URN)10.1109/NORCHIP.2015.7364416 (DOI)000380441400063 ()978-1-4673-6576-5 (ISBN)
Conference
2015 NORCAS conference, IEEE Nordic Circuits and Systems Conference, 26-28 October, Oslo, Norway
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-16Bibliographically approved
7. Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
Open this publication in new window or tab >>Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
2014 (English)In: Mixed Design of Integrated Circuits and Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Poland, 2014, 185-188 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents the design of a single-ended amplifier in 1.8~V, 180 nm CMOS process forbuffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffersuch as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation  achieves worst-case settling time of 19.3~ns andcurrent consumption of 66~$\mu$A while occupying an area of (19.2~$\mu$m $\times$ 19.2~$\mu$m).

Place, publisher, year, edition, pages
Poland: , 2014
Keyword
SAR ADC, Reference voltage buffer, DAC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-106913 (URN)10.1109/MIXDES.2014.6872182 (DOI)000345852100036 ()2-s2.0-84906699621 (Scopus ID)978-83-63578-04-6 (ISBN)
Conference
21st International Conference, Mixed Design of Integrated Circuits and Systems (MIXDES 2014), June 19-21, 2014, Lublin, Poland
Available from: 2014-05-26 Created: 2014-05-26 Last updated: 2015-11-18
8. Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
Open this publication in new window or tab >>Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, 381-384 p.Conference paper, Oral presentation only (Refereed)
Abstract [en]

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
Series
International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-87996 (URN)10.1109/ISCAS.2013.6571860 (DOI)000332006800094 ()978-1-4673-5760-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-01-28 Created: 2013-01-28 Last updated: 2015-11-18
9. An Analog Receiver Front-End for Capacitive Body-Coupled Communication
Open this publication in new window or tab >>An Analog Receiver Front-End for Capacitive Body-Coupled Communication
2012 (English)In: NORCHIP, 2012, IEEE , 2012, 1-4 p.Conference paper, Poster (with or without abstract) (Other academic)
Abstract [en]

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

Place, publisher, year, edition, pages
IEEE, 2012
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-84302 (URN)10.1109/NORCHP.2012.6403137 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
Conference
30th Norchip Conference 2012, The Nordic Microelectronics event, 12-13 November 2012, Copenhagen, Denmark
Available from: 2012-10-04 Created: 2012-10-04 Last updated: 2015-11-26Bibliographically approved

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