Design of a Sub-mW Front-End Amplifier for Capacitive BCC Receiver in 65 nm CMOS
2015 (English)Manuscript (preprint) (Other academic)
A low power front-end fully differential operational transconductance amplifier (OTA) has been designed in 65 nm CMOS technology which is suitable to receive low data rates upto 300 kbps for capacitive body coupled communication (BCC) channel. The current shunt current mirror OTA topology has been utilized in open loop configuration in the context of digital baseband architecture on the receiver side. The simulated resuts show that OTA achieves unity gain bandwidth (UGBW) of 200 MHz, dc gain of 40 dB, phase margin of 45 degree and rms integrated noise of 130 μV between 10 kHz to 150 MHz for 1.5 pF load capacitance and power consumption of approximately 250 μW. The OTA achieves high CMRR and PSRR (due to positive supply) of more than 120 dB at 100 Hz.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering Computer Science
IdentifiersURN: urn:nbn:se:liu:diva-122837OAI: oai:DiVA.org:liu-122837DiVA: diva2:874199