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A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Faculty of Science & Engineering.
2015 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, ISSN 0923-8174, Vol. 31, no 5, 503-523 p.Article in journal (Refereed) Published
Abstract [en]

n a modern three-dimensional integrated circuit (3D IC), vertically stacked dies are interconnected using through silicon vias. 3D ICs are subject to undesirable temperature-cycling phenomena such as through silicon via protrusion as well as void formation and growth. These cycling effects that occur during early life result in opens, resistive opens, and stress induced carrier mobility reduction. Consequently these early-life failures lead to products that fail shortly after the start of their use. Artificially-accelerated temperature cycling, before the manufacturing test, helps to detect such early-life failures that are otherwise undetectable. A test-ordering based temperature-cycling acceleration technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration methods. All these result in a reduction in the overall test costs. The proposed method is a test-ordering and schedule based solution that enforces the required temperature cycling effect and simultaneously performs the tests whenever appropriate. Experimental results demonstrate the efficiency of the proposed technique.

Place, publisher, year, edition, pages
2015. Vol. 31, no 5, 503-523 p.
Keyword [en]
Temperature cycling test, Test scheduling, Test ordering, 3D stacked IC
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-123489DOI: 10.1007/s10836-015-5541-5ISI: 000366640800007OAI: oai:DiVA.org:liu-123489DiVA: diva2:885519
Available from: 2015-12-18 Created: 2015-12-18 Last updated: 2016-06-08

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The full text will be freely available from 2016-11-16 00:00
Available from 2016-11-16 00:00

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Publisher's full texthttp://link.springer.com/article/10.1007%2Fs10836-015-5541-5

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Aghaee, NimaPeng, ZeboEles, Petru
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ESLAB - Embedded Systems LaboratoryFaculty of Science & Engineering
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ReferencesLink to record
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