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High-Throughput Trellis Processor for Multistandard FEC Decoding
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. Beijing Institute Technology, Peoples R China.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. Beijing Institute Technology, Peoples R China.
2015 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 12, 2757-2767 p.Article in journal (Refereed) PublishedText
Abstract [en]

Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unified forward-backward recursion kernel with an eight-state parallel trellis structure is proposed. Based on the kernel, a datapath for multialgorithm and a shared memory subsystem are introduced. The flexibility and the compatibility are guaranteed by a programmable decoding flow and the trellis decoding instruction set. Synthesis results show that the area consumption is 2.12 mm(2) (65 nm). TASIP provides trimode FEC decoding ability with the throughput of 533, 186, and 225 Mb/s for LDPC, turbo, and 64 states CC under the clock frequency of 200 MHz, which outperforms other trimode proposals both in area efficiency and recursion efficiency. TASIP provides high-throughput decoding for current standards, including 3rd Generation Partnership Project-Long Term Evolution, 802.16e, and 802.11n, with unified architecture and high compatibility.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2015. Vol. 23, no 12, 2757-2767 p.
Keyword [en]
Application-specific instruction-set processor (ASIP); forward-backward recursion (FBR); multistandard forward error correction (FEC); single instruction multiple data (SIMD); trellis decoding
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-123513DOI: 10.1109/TVLSI.2014.2382108ISI: 000365206300001OAI: oai:DiVA.org:liu-123513DiVA: diva2:886289
Note

Funding Agencies|National High-Tech Research and Development Program (863 Program) of China [2014AA01A705]

Available from: 2015-12-22 Created: 2015-12-21 Last updated: 2016-01-11Bibliographically approved

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Wu, ZhenzhiLiu, Dake
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ReferencesLink to record
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