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A Reconfigurable Framework for Performance Enhancement with Dynamic FPGA Configuration Prefetching
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
2015 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 35, no 1, 100-113 p.Article in journal (Refereed) Published
Abstract [en]

Many modern applications exhibit a dynamic and nonstationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable field programmable gate array architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx’s commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive application programming interface, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the smallest univalue segment assimilating nucleus image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-the-art prefetching algorithms, with only a minor energy overhead.

Place, publisher, year, edition, pages
2015. Vol. 35, no 1, 100-113 p.
Keyword [en]
Dynamic configuration prefetching, FPGA, dynamic configuration prefetching, field programmable gate array (FPGA), partial reconfiguration, self-reconfiguring and adaptive platform
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-123741DOI: 10.1109/TCAD.2015.2448694ISI: 000367338300008OAI: oai:DiVA.org:liu-123741DiVA: diva2:892805
Available from: 2016-01-11 Created: 2016-01-11 Last updated: 2016-02-02Bibliographically approved

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Lifa, AdrianEles, PetruPeng, Zebo
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ReferencesLink to record
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