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Efficient Integrated Circuits for Wideband Wireless Transceivers
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II.

The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2–5.2 dB, out-of-band IIP3 > +17 dBm and blocker P1dB > +5 dBm over a frequency range of 0.5–3 GHz.

The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging them becomes increasingly challenging. The degradation in performance or the drift from the optimal operation points may cause systems to fail. To prevent this effect and ensure acceptable performance in the presence of process, voltage and temperature variations (PVT), test and calibration of the RF ICs become indispensable. A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is proposed. Gain-boosting and sub-ranging techniques are applied to the detection circuit to increase the gain over the full range of input amplitudes without compromising the input impedance. A technique suitable for on-chip third/second-order intercept  point (IP3/IP2) test by embedded RF detectors is also introduced.

Part II comprises the design and analysis of high-speed switched-capacitor (SC) DACs for 60-GHz radio transmitters. The digital-to-analog converter (DAC) is one of the fundamental building blocks of transmitters. SC DACs offer several advantages over the current-steering DAC architecture. Specifically, lower capacitor mismatch helps the SC DAC to achieve higher linearity. The switches in the SC DAC are realized by MOS transistors in the triode region which substantially relaxes the voltage headroom requirement. Consequently, SC DACs can be implemented using lower supply voltages in advanced CMOS process nodes compared to their currentsteering counterparts. The first work in Part II analyzes the factors limiting the performance of capacitive pipeline DACs. It is shown that the DAC performance is  limited mainly by the clock feed-through and settling effects in the SC  arrays while the impact of capacitor mismatch and kT/C noise are found to be negligible. Based on this analysis, the second work in Part II proposes the split-segmented SC array DAC to overcome the clock feed-through problem since this topology eliminates pipelined charge propagation. Implemented in 65-nm CMOS, the 12-bit SC DAC achieves a Spurious Free Dynamic Range (SFDR) greater than 44 dB within the input signal bandwidth (BW) of 1 GHz with on-chip memory embedded for digital data generation. Power dissipation is 50 mW from 1.2 V supply. Similar performance is achieved with a lower supply voltage (0.9 V) which shows the scalability of the SC DAC for more advanced CMOS technologies. Furthermore, the proposed SC DAC satisfies the spectral mask of the IEEE 802.11ad WiGig standard with a second-order reconstruction filter and hence it can be used for the 60-GHz radio baseband.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2016. , 146 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1722
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Communication Systems
Identifiers
URN: urn:nbn:se:liu:diva-124006ISBN: 978-91-7685-904-9 (print)OAI: oai:DiVA.org:liu-124006DiVA: diva2:895024
Public defence
2016-02-26, Transformen, Hus B, Campus Valla, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2016-01-18 Created: 2016-01-18 Last updated: 2016-04-07Bibliographically approved
List of papers
1. Analysis and design of low noise transconductance amplifier for selective receiver front-end
Open this publication in new window or tab >>Analysis and design of low noise transconductance amplifier for selective receiver front-end
2015 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, 361-372 p.Article in journal (Refereed) Published
Abstract [en]

Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

Place, publisher, year, edition, pages
Springer, 2015
Keyword
Low-noise transconductance amplifier (LNTA); Highly linear LNA; Wideband LNA; SAW-less receiver; Wideband selective RF front-end
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-122187 (URN)10.1007/s10470-015-0629-5 (DOI)000361984600014 ()
Available from: 2015-10-26 Created: 2015-10-23 Last updated: 2017-12-01Bibliographically approved
2. Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
Open this publication in new window or tab >>Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, 421-425 p.Article in journal (Refereed) Published
Abstract [en]

In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

Keyword
SAW-less receiver, N-path filter, wideband selective RF front-end
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112879 (URN)10.1109/TCSII.2014.2385213 (DOI)000353636400001 ()
Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05Bibliographically approved
3. Wideband RF Detector Design for High Performance On-Chip Test
Open this publication in new window or tab >>Wideband RF Detector Design for High Performance On-Chip Test
2012 (English)In: NORCHIP 2012, IEEE , 2012, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.

Place, publisher, year, edition, pages
IEEE, 2012
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-86345 (URN)10.1109/NORCHP.2012.6403140 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
Conference
IEEE NORCHIP 2012, 12-13 November 2012, Copenhagen, Denmark
Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2016-01-18
4. Focused Calibration for Advanced RF Test with Embedded RF Detectors
Open this publication in new window or tab >>Focused Calibration for Advanced RF Test with Embedded RF Detectors
2013 (English)In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

Place, publisher, year, edition, pages
IEEE, 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-97268 (URN)10.1109/ECCTD.2013.6662259 (DOI)9783000437854 (ISBN)9783000434303 (ISBN)
Conference
21st European Conference on Circuit Theory and Design (ECCTD), September 8-12, Dresden, Germany
Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2016-01-18Bibliographically approved
5. Design and Analysis of High Speed Capacitive Pipeline DACs
Open this publication in new window or tab >>Design and Analysis of High Speed Capacitive Pipeline DACs
2014 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, 359-374 p.Article in journal (Refereed) Published
Abstract [en]

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

Keyword
capacitive DAC, high speed DAC, highly linear output driver
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-105516 (URN)10.1007/s10470-014-0350-9 (DOI)000342079400005 ()
Available from: 2014-03-25 Created: 2014-03-25 Last updated: 2017-12-05
6. A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS
Open this publication in new window or tab >>A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS
(English)Manuscript (preprint) (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Communication Systems
Identifiers
urn:nbn:se:liu:diva-124007 (URN)
Available from: 2016-01-18 Created: 2016-01-18 Last updated: 2016-01-18Bibliographically approved
7. Tunable Selective Receiver Front-End with Impedance Transformation Filtering
Open this publication in new window or tab >>Tunable Selective Receiver Front-End with Impedance Transformation Filtering
2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 5, 1071-1093 p.Article in journal (Refereed) Published
Abstract [en]

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is proposed in this paper. To achieve blocker rejection comparable to SAW filters, we use a two stage architecture based on a low noise trans-conductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying (LPV) model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate “back folding” by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept a chip design of a tunable RF front-end using 65 nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB,out of bandIIP3 > +17 dBm and blocker P1dB > +5 dBm over frequency range of 0.5—3 GHz.

Place, publisher, year, edition, pages
John Wiley & Sons, 2016
Keyword
SAW-less receiver; N-path filter; wideband selective RF front-end
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:liu:diva-122701 (URN)10.1002/cta.2125 (DOI)000376206000009 ()
Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-12-01Bibliographically approved
8. Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend
Open this publication in new window or tab >>Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend
2011 (English)In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, 825-828 p.Conference paper, Published paper (Refereed)
Abstract [en]

A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 - 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 <; -14 dB while the total power consumption is 3.9 mW for 1.2 V supply.

Place, publisher, year, edition, pages
Linköping, Sweden: IEEE conference proceedings, 2011
Keyword
Low-noise transconductance amplifier (LNTA), continuous-time ΣΔ RF frontend, high linearity LNA, wideband LNA
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-73028 (URN)10.1109/ECCTD.2011.6043832 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
Conference
20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011
Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2016-01-18Bibliographically approved
9. Highly linear open-loop output driver design for high speed capacitive DACs
Open this publication in new window or tab >>Highly linear open-loop output driver design for high speed capacitive DACs
2013 (English)In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-102930 (URN)10.1109/NORCHIP.2013.6702039 (DOI)9781479916474 (ISBN)
Conference
31st Norchip Conference, 11-12 November 2013, Vilnius, Lithuania
Available from: 2014-01-08 Created: 2014-01-08 Last updated: 2016-01-18Bibliographically approved

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Duong, Quoc-Tai

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