liu.seSearch for publications in DiVA
Change search
ReferencesLink to record
Permanent link

Direct link
Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-mu m CMOS
Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, 87-98 p.Article in journal (Refereed) PublishedText
Abstract [en]

This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-mu m CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 mu W. Core area of the ADC is 0.679 mm(2).

Place, publisher, year, edition, pages
Springer, 2016. Vol. 86, no 1, 87-98 p.
Keyword [en]
Pipelined SAR ADC; High resolution; OTA; Capacitive DAC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-124472DOI: 10.1007/s10470-015-0648-2ISI: 000367750900011OAI: oai:DiVA.org:liu-124472DiVA: diva2:899756
Available from: 2016-02-02 Created: 2016-02-01 Last updated: 2016-02-23

Open Access in DiVA

The full text will be freely available from 2016-10-18 00:00
Available from 2016-10-18 00:00

Other links

Publisher's full text

Search in DiVA

By author/editor
Chen, KairangHarikumar, PrakashAlvandpour, Atila
By organisation
Department of Electrical EngineeringFaculty of Science & EngineeringIntegrated Circuits and Systems
In the same journal
Analog Integrated Circuits and Signal Processing
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 695 hits
ReferencesLink to record
Permanent link

Direct link