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A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS
Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Catena Wireless Elect AB, Sweden.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, 244-248 p.Article in journal (Refereed) Published
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Abstract [en]

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2016. Vol. 63, no 3, 244-248 p.
Keyword [en]
Digital error correction; nonbinary-weighted; redundancy; successive approximation register (SAR) analog-to-digital converter (ADC); successive approximation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-127444DOI: 10.1109/TCSII.2015.2482618ISI: 000373136200004OAI: oai:DiVA.org:liu-127444DiVA: diva2:925214
Available from: 2016-04-30 Created: 2016-04-26 Last updated: 2016-04-30

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Zhang, DaiAlvandpour, Atila
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Electrical Engineering, Electronic Engineering, Information Engineering

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CiteExportLink to record
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Citation style
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