Challenging the Limits of FFT Performance on FPGAs
2014 (English)Conference paper (Refereed)
This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT generation tool has been developed. This tool is highly parameterizable and allows for generating FFTs with different FFT sizes and amount of parallelization. Experimental results for FFT sizes from 16 to 65536, and 4 to 64 parallel samples have been obtained. They show that even the largest FFT architectures fit well in today's FPGAs, achieving throughput rates from several GSamples/s to tens of GSamples/s.
Place, publisher, year, edition, pages
IEEE , 2014. 172-175 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-127974DOI: 10.1109/ISICIR.2014.7029571ISBN: 978-1-4799-4833-8OAI: oai:DiVA.org:liu-127974DiVA: diva2:927920
2014 International Symposium on Integrated Circuits (ISIC) 10-12 December 2014 Singapore