Experience Report: Memory Accesses for Avionic Applications and Operating Systems on a Multi-core Platform
2015 (English)Conference paper (Refereed)
The deployment of multi-core platforms in safety-critical avionic applications is hampered by the lack of means to ensure predictability when processes running on different cores can create interference effects, affecting worst-case execution time, due to shared memory accesses. One way to restrict these interferences is to allocate a budget for different processes prior to run-time and to monitor the adherence to this budget during run-time. While earlier works in adopting this approach seem promising, they focus on application level (user mode) accesses to shared memory and not the operating system accesses. In this paper we construct experiments for studying a multi-core platform running an ARINC 653 compliant operating system, and measure the impact of both application processes and operating system (supervisor mode) activities. In particular, as opposed to earlier works that considered networking applications, we select four avionic processes that exhibit different memory access patterns, namely, a navigation process, a matrix multiplication process, a math library process and an image processing one. The benchmarking on a set of avionic-relevant application processes shows that (a) the potential interference by the operating system cannot be neglected when allocating budgets that are to be monitored at run-time, and (b) the bounds for the allowed number of memory accesses should not always be based on the maximum measured count during profiling, which would lead to overly pessimistic budgets.
Place, publisher, year, edition, pages
2015. 153-160 p.
IdentifiersURN: urn:nbn:se:liu:diva-128173DOI: 10.1109/ISSRE.2015.7381809OAI: oai:DiVA.org:liu-128173DiVA: diva2:929734
IEEE International Symposium on Software Reliability Engineering, ISSRE.2-5 Nov. 2015 ,Gaithersbury, MD