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Time-Multiplexed Channel Switches for Dynamic Frequency Band Reallocation
Linköping University, Department of Electrical Engineering, Computer Engineering.
2016 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesisAlternative title
Tidsmultiplexade Kanalswitchar för Dynamisk Frekvensbandsreallokering (Swedish)
Abstract [en]

A partially parallel reconfigurable channel switch is constructed for use in DFBR. Its permutation can be changed while running without any interruption in the streams of data. Three approaches are tried: one based on asorting network, one based on memories and multiplexers and one based on a Clos network. Variants with the pattern stored in memories and in shift registers are tried. They are implemented in automatically generated Verilog and synthesized for an FPGA. Their cost in terms of area use, memory use and maximum clock frequency is compared and the results show that the Clos based approach is superior in all aspects and that pattern data should not be saved in shift registers. The work is open source and available for download at

Abstract [sv]

En delvis parallel och delvis seriell kanalswitch för användning inom DFBR skapas. Dess permutation kan ändras medan den kör utan avbrott i dataströmmen. Tre alternativ undersöks: ett baserat ett sorteringsnätverk, ett baserat på minnen och multiplexrar och ett som baseras på Clos-nätverk. Versioner med mönsterdata sparad i skiftregister och i minnen prövas. De implementeras i automatiskt genererad Verilog och synthesiseras för en FPGA. Deras kostnad i areaanvändning, minnesanvändning och maximal klockfrekvens jämförs. Resultaten visar i princip att Clos-nätverken är bäst i alla avseenden och att mönsterdata ska sparas i RAM-minnen och inte i skiftregister. Arbetet är open source och kan laddas ner från

Place, publisher, year, edition, pages
2016. , 43 p.
Keyword [en]
parallel, interleaver, bitonic, sorter, clos, network, sts, switch, dfbr, dynamic, frequency, band, reallocation
National Category
Computer Engineering
URN: urn:nbn:se:liu:diva-128793ISRN: LiTH-ISY-EX--16/4949--SEOAI: diva2:931953
Subject / course
Computer Engineering
2016-05-26, Algoritmen, 13:15 (English)
Available from: 2016-06-01 Created: 2016-05-31 Last updated: 2016-06-01Bibliographically approved

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Stenholm, Roland
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