SPARTA: A scheduling policy for thwarting differential power analysis attacksShow others and affiliations
2016 (English)In: 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE Press, 2016, p. 667-672Conference paper, Published paper (Refereed)
Abstract [en]
Embedded systems (ESs) have been widely used in various application domains. It is very important to design ESs that guarantee functional correctness of the system under strict timing constraints. Such systems are known as the real-time embedded systems (RTESs). More recently, RTESs started to be utilized in safety and reliability critical areas, which made the overlooked security issues, especially confidentiality of the communication, a serious problem. Differential power analysis attacks (DPAs) pose serious threats to confidentiality protection mechanisms, i.e., implementations of cryptographic algorithms, on embedded platforms. In this work, we present a scheduling policy, SPARTA, that thwarts DPAs. Theoretical guarantees and preliminary experimental results are presented to demonstrate the efficiency of the SPARTA scheduler.
Place, publisher, year, edition, pages
IEEE Press, 2016. p. 667-672
Series
Asia and South Pacific Design Automation Conference Proceedings, ISSN 2153-6961
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:liu:diva-129005DOI: 10.1109/ASPDAC.2016.7428088ISI: 000384642200117ISBN: 978-1-4673-9568-7 (print)OAI: oai:DiVA.org:liu-129005DiVA, id: diva2:934148
Conference
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). 25-28 Jan. 2016 Macau
2016-06-082016-06-082018-01-10