Minimax design and order estimation of FIR filters for extending the bandwidth of ADCs
2016 (English)In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS): Proceedings, Institute of Electrical and Electronics Engineers (IEEE), 2016, 2186-2189 p.Conference paper (Refereed)
The bandwidth of the sampling systems, especially for time-interleaved analog-to-digital converters, needs to be extended along with the rapid increase of the sampling rate. A digitally assisted technique becomes a feasible approach to extend the analog bandwidth, as it is impractical to implement the extension in analog circuits. This paper derives accurate order estimation formulas for the bandwidth extension filter, which is designed in the minimax sense with the ripple constraints as the design criteria. The derived filter order estimation is significant in evaluating the computational complexity from the viewpoint of the top-level system design. Moreover, with the proposed order estimates, one can conveniently obtain the minimal order that satisfies the given ripple constraints, which contributes to reducing the design time. Both the performance of the extension filter and its order estimation are illustrated and demonstrated through simulation examples.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016. 2186-2189 p.
, IEEE International Symposium on Circuits and Systems. Proceedings, ISSN 0271-4302 (Print), 2379-447X (Electronic)
IdentifiersURN: urn:nbn:se:liu:diva-131485DOI: 10.1109/ISCAS.2016.7539015ISBN: 978-1-4799-5341-7 (Electronic)ISBN: 978-1-4799-5340-0 (USB)ISBN: 978-1-4799-5342-4 (Print on Demand)OAI: oai:DiVA.org:liu-131485DiVA: diva2:973944
IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, Canada, May 22-25, 2016