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  • 1.
    A. Sani, Negar
    Linköping University, Department of Science and Technology, Physics and Electronics.
    M-PSK and M-QAM Modulation/Demodulation of UWB Signal Using Six-Port Correlator2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays high speed and high data rate communication are highly demanded. Consequently, wideband and high frequency transmitter and receivers should be designed. New transmitters and receivers should also have low power consumption, simple design and low manufacturing price in order to fulfill manufacturers’ requests for mass production. Having all above specifications, six-port correlator is a proper choice to be used as modulator and demodulator in transmitters and receivers.

    In this thesis the six-port correlator is introduced, modeled and simulated using Advanced Design System (ADS) software. A simple six-port transmitter/receiver system with a line of sight link is modeled and analyzed in BER, path length and noise terms. The modulation in this system is QAM, frequency is 7.5 GHz and symbol rate is 500 Msymbol/s.

    Furthermore two methods are proposed for high frequency and high symbol rate M-PSK and M-QAM modulation using six-port correlator. The 7.5 GHz modulators are modeled and simulated in ADS. Data streams generated by pseudo random bit generator with 1 GHz bandwidth are applied to modulators. Common source field effect transistors (FETs) with zero bias are used as controllable impedance termination to apply baseband data to modulator. Both modulators show good performance in M-PSK and M-QAM modulation.

  • 2.
    Aamir, Syed Ahmed
    Linköping University. Linköping University, Department of Electrical Engineering.
    A 65nm, Low Voltage, Fully Differential, SC Programmable Gain Amplifier for Video AFE2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Due to rapid growth of home entertainment consumer market, video technology has been continuously pushed to deliver sharper pictures with higher resolution. This has brought about stringent requirements on the video analog front end, which often coupled with the low power and low voltage regulations had to deal with short channel effects of the deep submicron CMOS processes.

    This thesis presents the design of a fully differential programmable gain amplifier, as a subcircuit of a larger video digitizing IC designed at division of Electronic Systems. The switched capacitor architecture of the PGA does not only buffer the signal, but performs compensation for the sync-tip of analog video signal.

    The pseudo differential OTA eliminates tail current source and maintains high signal swing and has efficient common mode feedforward mechanism. When coupled with a similar stage provides inherent common moode feedback without using an additional SC-CMFB block.

    The PGA has been implemented using a 65 nm digital CMOS process. Expected difficulties in a 1.2 V OTA design make themselves evident in 65 nm, which is why cascaded OTA structures were inevitable for attaining gain specification of 60 dB. Nested Miller compensation with a pole shifting source follower, stabilizes the multipole system. The final circuit attains up to 200 MHz bandwidth and maintains high output swing of 0.85 V. High slew rate and good common mode and power supply rejection are observed. Noise requirements require careful design of input differential stage. Although output source follower stabilized the system, it reduces significant bandwidth and adds to second order non-linearity.

  • 3.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS2010In: 17th IEEE International Conference on Electronics, Circuits, and Systems., www.ieee.org , 2010, 29-32 p.Conference paper (Refereed)
    Abstract [en]

    In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

  • 4.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS2010In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10, Tampere: www.ieee.org , 2010, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.

  • 5.
    Abbas, Muhammad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the Implementation of Integer and Non-Integer Sampling Rate Conversion2012Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The main focus in this thesis is on the aspects related to the implementation of integer and non-integer sampling rate conversion (SRC). SRC is used in many communication and signal processing applications where two signals or systems having different sampling rates need to be interconnected. There are two basic approaches to deal with this problem. The first is to convert the signal to analog and then re-sample it at the desired rate. In the second approach, digital signal processing techniques are utilized to compute values of the new samples from the existing ones. The former approach is hardly used since the latter one introduces less noise and distortion. However, the implementation complexity for the second approach varies for different types of conversion factors. In this work, the second approach for SRC is considered and its implementation details are explored. The conversion factor in general can be an integer, a ratio of two integers, or an irrational number. The SRC by an irrational numbers is impractical and is generally stated for the completeness. They are usually approximated by some rational factor.

    The performance of decimators and interpolators is mainly determined by the filters, which are there to suppress aliasing effects or removing unwanted images. There are many approaches for the implementation of decimation and interpolation filters, and cascaded integrator comb (CIC) filters are one of them. CIC filters are most commonly used in the case of integer sampling rate conversions and often preferred due to their simplicity, hardware efficiency, and relatively good anti-aliasing (anti-imaging) characteristics for the first (last) stage of a decimation (interpolation). The multiplierless nature, which generally yields to low power consumption, makes CIC filters well suited for performing conversion at higher rate. Since these filters operate at the maximum sampling frequency, therefore, are critical with respect to power consumption. It is therefore necessary to have an accurate and efficient ways and approaches that could be utilized to estimate the power consumption and the important factors that are contributing to it. Switching activity is one such factor. To have a high-level estimate of dynamic power consumption, switching activity equations in CIC filters are derived, which may then be used to have an estimate of the dynamic power consumption. The modeling of leakage power is also included, which is an important parameter to consider since the input sampling rate may differ several orders of magnitude. These power estimates at higher level can then be used as a feed-back while exploring multiple alternatives.

    Sampling rate conversion is a typical example where it is required to determine the values between existing samples. The computation of a value between existing samples can alternatively be regarded as delaying the underlying signal by a fractional sampling period. The fractional-delay filters are used in this context to provide a fractional-delay adjustable to any desired value and are therefore suitable for both integer and non-integer factors. The structure that is used in the efficient implementation of a fractional-delay filter is know as Farrow structure or its modifications. The main advantage of the Farrow structure lies in the fact that it consists of fixed finite-impulse response (FIR) filters and there is only one adjustable fractional-delay parameter, used to evaluate a polynomial with the filter outputs as coefficients. This characteristic of the Farrow structure makes it a very attractive structure for the implementation. In the considered fixed-point implementation of the Farrow structure, closed-form expressions for suitable word lengths are derived based on scaling and round-off noise. Since multipliers share major portion of the total power consumption, a matrix-vector multiple constant multiplication approach is proposed to improve the multiplierless implementation of FIR sub-filters.

    The implementation of the polynomial part of the Farrow structure is investigated by considering the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained and used to short list the suitable candidates. Most of these evaluation schemes require the explicit computation of higher order power terms. In the parallel evaluation of powers, redundancy in computations is removed by exploiting any possible sharing at word level and also at bit level. As a part of this, since exponents are additive under multiplication, an ILP formulation for the minimum addition sequence problem is proposed.

    List of papers
    1. Power Estimation of Recursive and Non-Recursive CIC Filters Implemented in Deep-Submicron Technology
    Open this publication in new window or tab >>Power Estimation of Recursive and Non-Recursive CIC Filters Implemented in Deep-Submicron Technology
    2010 (English)In: Proceedings of International Conference on Green Circuits and Systems (ICGCS), 2010, Date: 21-23 June, 2010, IEEE , 2010, 221-225 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    The power modeling of different realizations of cascaded integrator-comb (CIC) decimation filters has been a subject of several recent works. In this work we have extended these with modeling of leakage power, which is an important factor since the input sample rate may differ several orders of magnitude. Furthermore, we have pointed out the importance of the input wordlength on the comparison of recursive and nonrecursive implementations.

    Place, publisher, year, edition, pages
    IEEE, 2010
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-70451 (URN)10.1109/ICGCS.2010.5543063 (DOI)978-1-4244-6877-5 (ISBN)978-1-4244-6876-8 (ISBN)
    Conference
    International Conference on Green Circuits and Systems (ICGCS), June 21–23, Shanghai, China
    Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
    2. Switching Activity Estimation of CIC Filter Integrators
    Open this publication in new window or tab >>Switching Activity Estimation of CIC Filter Integrators
    2010 (English)In: Proceedings of Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010, Date:22-24 Sept. 2010, IEEE , 2010, 21-24 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, a method for estimation of the switching activity in integrators is presented. To achieve low power, it is always necessary to develop accurate and efficient methods to estimate the switching activity. The switching activities are then used to estimate the power consumption. In our work, the switching activity is first estimated for the general purpose integrators and then it is extended for the estimation of switching activity in cascaded integrators in CIC filters.

    Place, publisher, year, edition, pages
    IEEE, 2010
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-70452 (URN)10.1109/PRIMEASIA.2010.5604971 (DOI)978-1-4244-6736-5 (ISBN)978-1-4244-6735-8 (ISBN)
    Conference
    Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 22-24 September, Shanghai, China
    Note
    ©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. MUHAMMAD ABBAS and Oscar Gustafsson, Switching Activity Estimation of CIC Filter Integrators, 2010, Asia Pacific Conf. on Postgraduate Research in Microelectronics and Electronics, Shanghai, China. http://dx.doi.org/10.1109/PRIMEASIA.2010.5604971 Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
    3. Scaling of fractional delay filters based on the Farrow structure
    Open this publication in new window or tab >>Scaling of fractional delay filters based on the Farrow structure
    2009 (English)In: Proceedings of IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009, Piscataway: IEEE , 2009, 489-492 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work we consider scaling of fractional delay filters using the Farrow structure. Based on the observation that the subfilters approximate the Taylor expansion of a differentiator, we derive estimates of the L2-norm scaling values at the outputs of each subfilter as well as at the inputs of each delay multiplier. The scaling values can then be used to derive suitable wordlengths in a fixed-point implementation.

    Place, publisher, year, edition, pages
    Piscataway: IEEE, 2009
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-51070 (URN)10.1109/ISCAS.2009.5117792 (DOI)000275929800123 ()978-1-4244-3827-3 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems, 24-27 May 2009, Taipei,Taiwan
    Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2015-03-11Bibliographically approved
    4. Computational and Implementation Complexity of Polynomial Evaluation Schemes
    Open this publication in new window or tab >>Computational and Implementation Complexity of Polynomial Evaluation Schemes
    2011 (English)In: Proceedings of NORCHIP, 2011 Date:14-15 Nov. 2011, IEEE conference proceedings, 2011, 1-6 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, we consider the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained. These can then be used to short list suitable candidates for an implementation given the specifications. Not only multiplications are considered, but they are divided into data-data multiplications, squarers, and data-coefficient multiplications, as the latter can be optimized depending on implementation architecture and application.

    Place, publisher, year, edition, pages
    IEEE conference proceedings, 2011
    Keyword
    Adders, Computer architecture, Delay, Filtering algorithms, ISO, Pipeline processing, Polynomials
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-73935 (URN)10.1109/NORCHP.2011.6126735 (DOI)978-1-4577-0515-1 (ISBN)978-1-4577-0514-4 (ISBN)
    Conference
    NORCHIP 2011. The Nordic Microelectronics event, 29th Norchip Conference 14-15 November 2011, Lund, Sweden
    Available from: 2012-01-17 Created: 2012-01-17 Last updated: 2015-03-11Bibliographically approved
    5. Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy
    Open this publication in new window or tab >>Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy
    2010 (English)In: Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 / [ed] Michael B. Matthews, Washington, DC, USA: IEEE Computer Society , 2010, 1168-1172 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.

    Place, publisher, year, edition, pages
    Washington, DC, USA: IEEE Computer Society, 2010
    Series
    Asilomar Conference on Signals, Systems and Computers. Conference Record, ISSN 1058-6393
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-70453 (URN)10.1109/ACSSC.2010.5757714 (DOI)978-1-4244-9722-5 (ISBN)
    Conference
    Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 , Pacific Grove, CA, USA
    Available from: 2011-09-20 Created: 2011-09-08 Last updated: 2015-03-11Bibliographically approved
    6. Integer Linear Programming Modeling of Addition Sequences With Additional Constraints for Evaluation of Power Terms
    Open this publication in new window or tab >>Integer Linear Programming Modeling of Addition Sequences With Additional Constraints for Evaluation of Power Terms
    (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    In this work, an integer linear programming (ILP) based model is proposed for the computation of a minimal cost addition sequence for a given set of integers. Since exponents are additive under multiplication, the minimal length addition sequence will provide an optimal solution for the evaluation of a requested set of power terms. This in turn finds application in, e.g., window-based exponentiation for cryptography and polynomial evaluation. Not only is an optimal model proposed, the model is extended to consider different costs for multipliers and squarers as well as controlling the depth of the resulting addition sequence.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-73936 (URN)
    Available from: 2012-01-17 Created: 2012-01-17 Last updated: 2015-03-11Bibliographically approved
    7. Switching Activity Estimation of DDFS Phase Accumulators
    Open this publication in new window or tab >>Switching Activity Estimation of DDFS Phase Accumulators
    (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    In this letter, equations for the one’s probability and switching activities for direct digital frequency synthesis (DDFS) phase accumulators are derived. These results are useful for obtaining good accuracy estimated of both leakage and dynamic power consumption for the phase accumulator and the phase-to-magnitude converter.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-73937 (URN)
    Available from: 2012-01-17 Created: 2012-01-17 Last updated: 2015-03-11Bibliographically approved
  • 6.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 4, 926-937 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.

  • 7.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Scaling of fractional delay filters based on the Farrow structure2009In: Proceedings of IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009, Piscataway: IEEE , 2009, 489-492 p.Conference paper (Refereed)
    Abstract [en]

    In this work we consider scaling of fractional delay filters using the Farrow structure. Based on the observation that the subfilters approximate the Taylor expansion of a differentiator, we derive estimates of the L2-norm scaling values at the outputs of each subfilter as well as at the inputs of each delay multiplier. The scaling values can then be used to derive suitable wordlengths in a fixed-point implementation.

  • 8.
    Abbasi, Muneeb Mehmood
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Jabbar, Mohammad Abdul
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Design and Performance Analysis of Low-Noise Amplifier with Band-Pass Filter for 2.4-2.5 GHz2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Low power wireless electronics is becoming more popular due to durability, portability and small dimension. Especially, electronic devices in instruments, scientific and medical (ISM) band is convenient from the spectrum regulations and technology availability point of view. In the communication engineering society, to make a robust transceiver is always a matter of challenges for the better performance.

    However, in this thesis work, a new approach of design and performance analysis of Low-Noise Amplifier with Band-Pass filter is performed at 2.45 GHz under the communication electronics research group of Institute of Science and Technology (ITN). Band-Pass Filtered Low-Noise Amplifier is designed with lumped components and transmission lines. Performances of different designs are compared with respect to noise figure, gain, input and output reflection coefficient. In the design process, a single stage LNA is designed with amplifier, ATF-58143. Maximally flat band-pass (BPF) filters were designed with lumped components and distributed elements. Afterwards, BPF is integrated with the LNA at the front side of LNA to get a compact Band-Pass Filtered Low-Noise Amplifier with good performance.

    Advanced Design System (ADS) tool was used for design and simulation, and each design was tuned to get the optimum value for noise figure, gain and input reflection coefficient. LNA stand-alone gives acceptable value of noise figure and gain but the bandwidth was too wide compared to specification. Band-Pass Filtered Low-Noise Amplifier with lumped components gives also considerable values of noise and gain. But the gain was not so flat and the bandwidth was also wide. Then, Band-Pass Filtered Low-Noise Amplifier was designed with transmission lines where the optimum value of noise figure and gain was found. The gain was almost flat over the whole band, i.e., 2.4-2.5 GHz compared to LNA stand-alone and Band-Pass Filtered Low-Noise Amplifier designed with lumped components. It is observed that deviations of results from schematic to layout level are considerable, i.e., electromagnetic simulation is needed to predict the Band-Pass Filtered Low-Noise Amplifier performance.

    Prototype of LNA, Band-Pass Filtered Low-Noise Amplifier with lumped and transmission lines are made at ITN’s PCB laboratory. Due to unavailability of exact values of Murata components and for some other technical reasons, the measured values of Band-Pass Filtered Low-Noise Amplifier with lumped components and transmission lines are deviated compared to predicted values from simulation.

  • 9.
    Abdollahi Sani, Negar
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Robertsson, Mats
    Linköping University, Department of Science and Technology. Linköping University, The Institute of Technology.
    Cooper, Philip
    De La Rue Plc, Overton, Hampshire, UK .
    Wang, Xin
    Acreo AB, Norrköping, Sweden.
    Svensson, Magnus
    Acreo AB, Norrköping, Sweden.
    Andersson Ersman, Peter
    Acreo AB, Norrköping, Sweden.
    Norberg, Petronella
    Acreo AB, Norrköping, Sweden.
    Nilsson, Marie
    Acreo AB, Norrköping, Sweden.
    Nilsson, David
    Acreo AB, Norrköping, Sweden.
    Liu, Xianjie
    Linköping University, Department of Physics, Chemistry and Biology, Surface Physics and Chemistry. Linköping University, The Institute of Technology.
    Hesselbom, Hjalmar
    Hesselbom Innovation and Development HB, Huddinge, Sweden .
    Akesso, Laurent
    De La Rue Plc, Overton, Hampshire, UK .
    Fahlman, Mats
    Linköping University, Department of Physics, Chemistry and Biology, Surface Physics and Chemistry. Linköping University, The Institute of Technology.
    Crispin, Xavier
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Engquist, Isak
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Berggren, Magnus
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology. Acreo AB, Norrköping, Sweden.
    Gustafsson, Goran
    Acreo AB, Norrköping, Sweden.
    All-printed diode operating at 1.6 GHz2014In: Proceedings of the National Academy of Sciences of the United States of America, ISSN 0027-8424, E-ISSN 1091-6490, Vol. 111, no 33, 11943-11948 p.Article in journal (Refereed)
    Abstract [en]

    Printed electronics are considered for wireless electronic tags and sensors within the future Internet-of-things (IoT) concept. As a consequence of the low charge carrier mobility of present printable organic and inorganic semiconductors, the operational frequency of printed rectifiers is not high enough to enable direct communication and powering between mobile phones and printed e-tags. Here, we report an all-printed diode operating up to 1.6 GHz. The device, based on two stacked layers of Si and NbSi2 particles, is manufactured on a flexible substrate at low temperature and in ambient atmosphere. The high charge carrier mobility of the Si microparticles allows device operation to occur in the charge injection-limited regime. The asymmetry of the oxide layers in the resulting device stack leads to rectification of tunneling current. Printed diodes were combined with antennas and electrochromic displays to form an all-printed e-tag. The harvested signal from a Global System for Mobile Communications mobile phone was used to update the display. Our findings demonstrate a new communication pathway for printed electronics within IoT applications.

  • 10.
    Abdollahi Sani, Negar
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Wang, Xin
    Acreo Swedish ICT AB, Sweden.
    Granberg, Hjalmar
    INNVENTIA AB, Sweden.
    Andersson Ersman, Peter
    Acreo Swedish ICT AB, Sweden.
    Crispin, Xavier
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Dyreklev, Peter
    Acreo Swedish ICT AB, Sweden.
    Engquist, Isak
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Gustafsson, Göran
    Acreo Swedish ICT AB, Sweden.
    Berggren, Magnus
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Flexible Lamination-Fabricated Ultra-High Frequency Diodes Based on Self-Supporting Semiconducting Composite Film of Silicon Micro-Particles and Nano-Fibrillated Cellulose2016In: Scientific Reports, ISSN 2045-2322, E-ISSN 2045-2322, Vol. 6, no 28921Article in journal (Refereed)
    Abstract [en]

    Low cost and flexible devices such as wearable electronics, e-labels and distributed sensors will make the future "internet of things" viable. To power and communicate with such systems, high frequency rectifiers are crucial components. We present a simple method to manufacture flexible diodes, operating at GHz frequencies, based on self-adhesive composite films of silicon micro-particles (Si-mu Ps) and glycerol dispersed in nanofibrillated cellulose (NFC). NFC, Si-mu Ps and glycerol are mixed in a water suspension, forming a self-supporting nanocellulose-silicon composite film after drying. This film is cut and laminated between a flexible pre-patterned Al bottom electrode and a conductive Ni-coated carbon tape top contact. A Schottky junction is established between the Al electrode and the Si-mu Ps. The resulting flexible diodes show current levels on the order of mA for an area of 2 mm(2), a current rectification ratio up to 4 x 10(3) between 1 and 2 V bias and a cut-off frequency of 1.8 GHz. Energy harvesting experiments have been demonstrated using resistors as the load at 900 MHz and 1.8 GHz. The diode stack can be delaminated away from the Al electrode and then later on be transferred and reconfigured to another substrate. This provides us with reconfigurable GHz-operating diode circuits.

  • 11.
    Abdul Aziz Hasan Ali, Aamir
    et al.
    Linköping University, Department of Science and Technology, Communications and Transport Systems. Linköping University, The Institute of Technology.
    Shahzad, Muhammad Adil
    Linköping University, Department of Science and Technology, Communications and Transport Systems. Linköping University, The Institute of Technology.
    A Joint Subcarrier/Power allocation Scheme for OFDMA-based Cellular Networks2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The assignment of this master thesis consists of initiating power, subcarrier allocation in a dynamic FFR based scheme designed for multi-cell OFDMA networks and to enhance the throughput of all center users in bandwidth hungry borrower cells (overloaded cells) which was previously degraded by original FFR3 scheme as a result of partitioning of system bandwidth into center and edge bands respectively. The method uses band borrowing to compensate center user’s throughput loss in a semi and fully overloaded system. The scheme uses dynamic programming method (0/1 knapsack problem) to bargain an edge band on various power levels and tends to check the best combination (power and sub-carrier) which the system can utilize while still maintaining acceptable throughput loss for the users at the edge of the neighboring cell (lender cell).

    The algorithm consists of generating a borrowing request to neighboring cells for utilizing their edge bands by the overloaded borrower cell if their average center user throughput reaches below a minimum threshold value set in the system. The borrowing method uses 0/1 knapsack problem to capture an edge band based on limiting factors of total cost in average throughput losses by neighbors (Ci) and Un (tolerable mean user edge user throughput loss by lending cell). While solving knapsack problem the lender (neighbors) will check Ci and Un before granting the right to use its edge band. The later stage requires reducing subcarrier power level in order to utilize the lenders edge band using "soft borrower" mode. The borrowed sub-carriers will be activated take power from the original center band sub-carriers of the overloaded cell by taking into account the interference between the lender and the borrower. In case of negative (0) reply from the lender cell after the first request, multiple requests are generated at reduce power level at every step to order to acquire more bands. If a neighbor has band borrowing requests from multiple overloaded base stations, the band will be granted to the one which gives minimal loss in terms of throughput to the lender cell.

    The simulation results are analyzed w.r.t reuse-1 and FFR3 scheme of a multi cell regular and irregular scenarios comprising of lightly to heavily overloaded cells with various subcarrier allocation patterns. An overhead and time assessment is also presented between borrower and lender cells. Simulation results show an increase of 60% in center user’s throughput w.r.t original FFR3 scheme with an acceptable loss of 18% at the edges in complex overloaded scenarios while the overall system throughout increases by 35%.

  • 12.
    Aberger, Martin
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Effects of Nonlinearities in Black Box Identification of an Industrial Robot2000Report (Other academic)
    Abstract [en]

    This paper discusses effects of nonlinearities in black box identification of one axis of a robot. The used data come from a commercial ABB robot, IRB1400. A three-mass flexible model for the robot was built in MathModelica. The nonlinearities in the model are nonlinear friction and backlash in the gear box.

  • 13.
    Abidin, Aysajan
    et al.
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, The Institute of Technology.
    Larsson, Jan-Åke
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, The Institute of Technology.
    Direct proof of security of Wegman-Carter authentication with partially known key2014In: Quantum Information Processing, ISSN 1570-0755, E-ISSN 1573-1332, Vol. 13, no 10, 2155-2170 p.Article in journal (Refereed)
    Abstract [en]

    Information-theoretically secure (ITS) authentication is needed in Quantum Key Distribution (QKD). In this paper, we study security of an ITS authentication scheme proposed by Wegman& Carter, in the case of partially known authentication key. This scheme uses a new authentication key in each authentication attempt, to select a hash function from an Almost Strongly Universal2 hash function family. The partial knowledge of the attacker is measured as the trace distance between the authentication key distribution and the uniform distribution; this is the usual measure in QKD. We provide direct proofs of security of the scheme, when using partially known key, first in the information-theoretic setting and then in terms of witness indistinguishability as used in the Universal Composability (UC) framework. We find that if the authentication procedure has a failure probability ε and the authentication key has an ε´ trace distance to the uniform, then under ITS, the adversary’s success probability conditioned on an authentic message-tag pair is only bounded by ε +|Ƭ|ε´, where |Ƭ| is the size of the set of tags. Furthermore, the trace distance between the authentication key distribution and the uniform increases to |Ƭ|ε´ after having seen an authentic message-tag pair. Despite this, we are able to prove directly that the authenticated channel is indistinguishable from an (ideal) authentic channel (the desired functionality), except with probability less than ε + ε´. This proves that the scheme is (ε + ε´)-UC-secure, without using the composability theorem.

  • 14.
    Abidin, Aysajan
    et al.
    Linköping University, Department of Electrical Engineering, Information Coding.
    Larsson, Jan-Åke
    Linköping University, Department of Electrical Engineering, Information Coding.
    New Universal Hash Functions2012In: Lecture Notes in Computer Science, Vol. 7242 / [ed] Frederik Armknecht and Stefan Lucks, Springer Berlin Heidelberg , 2012, 99-108 p.Conference paper (Refereed)
    Abstract [en]

    Universal hash functions are important building blocks for unconditionally secure message authentication codes. In this paper, we present a new construction of a class of Almost Strongly Universal hash functions with much smaller description (or key) length than the Wegman-Carter construction. Unlike some other constructions, our new construction has a very short key length and a security parameter that is independent of the message length, which makes it suitable for authentication in practical applications such as Quantum Cryptography.

  • 15.
    Abrahamsson, Henrik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering.
    Carlson, Peter
    Linköping University, The Institute of Technology.
    Robust Torque Control for Automated Gear Shifting in Heavy Duty Vehicles2008Independent thesis Advanced level (professional degree), 20 points / 30 hpStudent thesis
    Abstract [en]

    In an automated manual transmission it is desired to have zero torque in the transmission when disengaging a gear. This minimizes the oscillations in the driveline which increases the comfort and makes the speed synchronization easier. The automated manual transmission system in a Scania truck, called Opticruise, uses engine torque control to achieve zero torque in the transmission.In this thesis different control strategies for engine torque control are proposed in order to minimize the oscillations in the driveline and increase the comfort during a gear shift. A model of the driveline is developed in order to evaluate the control strategies. The main focus was to develop controllers that are easy to implement and that are robust enough to be used in different driveline configurations. This means that model dependent control strategies are not considered.A control strategy with a combination of a feedback from the speed difference between the output shaft speed and the wheel speed, and a feedforward with a linear ramp, showed very good performance in both simulations and tests in trucks. The amplitude of the oscillations in the output shaft speed after neutralengagement are halved compared to the results from the existing method in Scania trucks. The new concept is also more robust against initial conditions and time delay estimations.

  • 16.
    Abrahamsson, Per
    Linköping University, Department of Electrical Engineering.
    Combined Platform for Boost Guidance and Attitude Control for Sounding Rockets2004Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This report handles the preliminary design of a control system that includes both attitude control and boost control functionality for sounding rockets. This is done to reduce the weight and volume for the control system.

    A sounding rocket is a small rocket compared to a satellite launcher. It is used to launch payloads into suborbital trajectories. The payload consists of scientific experiments, for example micro-gravity experiments and astronomic observations. The boost guidance system controls the sounding rocket during the launch phase. This is done to minimize the impact dispersion. The attitude control system controls the payload during the experiment phase.

    The system that is developed in this report is based on the DS19 boost guidance system from Saab Ericsson Space AB. The new system is designed by extending DS19 with software and hardware. The new system is therefore named DS19+. Hardware wise a study of the mechanical and electrical interfaces and also of the system budgets for gas, mass and power for the system are done to determine the feasibility for the combined system.

    Further a preliminary design of the control software is done. The design has been implemented as pseudo code in MATLAB for testing and simulations. A simulation model for the sounding rocket andits surroundings during the experiment phase has also been designed and implemented in MATLAB. The tests and simulations that have been performed show that the code is suitable for implementation in the real system.

  • 17.
    Abrahamsson, Robin
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Kovalev, Anton
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Lindell, Johan
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Lövhall, Jakob
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Nordfors, Per
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Rydström, Simon
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Stoltz, Robert
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Utveckling av energioptimeringsprogrammet Humble: erfarenheter från projekt i programvaruutveckling2014Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [sv]

    Den här rapporten behandlar ett kandidatarbete som utfördes mot Institutionen för ekonomisk och industriell utveckling. Arbetet gick ut på att modernisera det existerande programmet MODEST som använts för att beräkna optimala energisystem. Moderniseringen gjordes genom att skapa programmet Humble, vars funktionalitet bygger på MODEST.

    I den här rapporten beskrivs hur program kan utvecklas för att de ska vara enkla att använda, samt hur de kan konstrueras för att möjliggöra vidareutveckling. Dessa aspekter framställdes av kunden som viktiga i projektet.

    Gruppens tillvägagångssätt för att utveckla programmet förklaras och en överskådlig bild över den arkitektur som använts ges. De erfarenheter som gruppen förskaffat sig under projektet beskrivs och reflekteras över. Detta gäller såväl tekniska erfarenheter som erfarenheter kopplade till projektprocessen. Gruppmedlemmarnas personliga erfarenheter kopplade till de roller de haft i projektet beskrivs i individuellt skrivna delar.

    Slutligen diskuteras projektet och hur resultatet har uppnåtts, varefter slutsatser kopplade till frågeställningarna dras. Dessa slutsatser är att prototypning och användbarhetstester är effektiva metoder för att skapa program som är enkla att använda, samt att program som tillämpar tydligt dokumenterade designmönster och är modulärt uppbyggda möjliggör vidareutveckling.

  • 18.
    Abrahamsson, Sebastian
    et al.
    Linköping University, Department of Electrical Engineering.
    Råbe, Markus
    Linköping University, Department of Electrical Engineering.
    An FPGA implementation of a modulator for digital terrestrial television according to the DTMB standard2010Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation.

    This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard.

    The system is written in VHDL and is intended for implementation on an FPGA.

  • 19.
    Abrahamsson, Thomas
    et al.
    Saab Military Aircraft, Sweden.
    Andersson, Magnus
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    McKelvey, Tomas
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    A Finite Element Model Updating Formulation Using Frequency Responses and Eigenfrequencies1996Report (Other academic)
    Abstract [en]

    A novel frequency and modal domain formulation of the model updating problem is presented. Deviations in discrete frequency responses and eigenfrequencies, between the model to be updated and a reference model, constitute the criterion function. A successful updating thus results in a model with the reference's input-output relations at selected fre- quencies. The formulation is demonstrated to produce a criterion function with a global minimum having a large domain of attraction with respect to stiffness and mass variations. The method relies on mode grouping and uses a new extended modal assurance criterion number (eMAC) for identifying related modes. A quadratic objective with inexpensive evaluation of approximate Hessians give a rapid convergence to a minimum by the use of a regularized Gauss-Newton method. Physical bounds on parameters and complementary data, such as structural weight, are treated by imposing set constraints and linear equality constraints. Efficient function computation is obtained by model reduction using a moderately sized base of modes which is recomputed during the minimization. Statistical properties of updated parameters are discussed. A verification example show the performance of the method.

  • 20.
    Abrahamsson, Tomas
    et al.
    Saab Military Aircraft, Sweden.
    McKelvey, Tomas
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Ljung, Lennart
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    A Study of some Approaches to Vibration Data Analysis1993Report (Other academic)
    Abstract [en]

    Using data from extensive vibrational tests of the new aircraft Saab 2000 three different methods for vibration analysis are studied. These methods are ERA (eigensystem realization algorithm), N4SID (a subspace method) and PEM (prediction error approach). We find that both the ERA and N4SID methods give good initial model parameter estimates that can be further improved by the use of PEM. We also find that all methods give good insights into the vibrational modes.

  • 21.
    Abrikosov, Igor
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Theoretical Physics. Linköping University, Faculty of Science & Engineering. National University of Science and Technology MISIS, Russia.
    Ponomareva, A. V.
    National University of Science and Technology MISIS, Russia.
    Steneteg, Peter
    Linköping University, Department of Science and Technology, Media and Information Technology. Linköping University, Faculty of Science & Engineering.
    Barannikova, S. A.
    National University of Science and Technology MISIS, Russia; National Research Tomsk State University, Russia; SB RAS, Russia.
    Alling, Björn
    Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics. Linköping University, Faculty of Science & Engineering.
    Recent progress in simulations of the paramagnetic state of magnetic materials2016In: Current opinion in solid state & materials science, ISSN 1359-0286, E-ISSN 1879-0348, Vol. 20, no 2, 85-106 p.Article, review/survey (Refereed)
    Abstract [en]

    We review recent developments in the field of first-principles simulations of magnetic materials above the magnetic order disorder transition temperature, focusing mainly on 3d-transition metals, their alloys and compounds. We review theoretical tools, which allow for a description of a system with local moments, which survive, but become disordered in the paramagnetic state, focusing on their advantages and limitations. We discuss applications of these theories for calculations of thermodynamic and mechanical properties of paramagnetic materials. The presented examples include, among others, simulations of phase stability of Fe, Fe-Cr and Fe-Mn alloys, formation energies of vacancies, substitutional and interstitial impurities, as well as their interactions in Fe, calculations of equations of state and elastic moduli for 3d-transition metal alloys and compounds, like CrN and steels. The examples underline the need for a proper treatment of magnetic disorder in these systems. (C) 2015 Elsevier Ltd. All rights reserved.

    The full text will be freely available from 2018-04-01 13:15
  • 22.
    Acevedo, Miguel
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    FPGA-Based Hardware-In-the-Loop Co-Simulator Platform for SystemModeler2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis proposes and implements a flexible platform to perform Hardware-In-the-Loop (HIL) co-simulation using a Field-Programmable-Gate-Array (FPGA). The HIL simulations are performed with SystemModeler working as a software simulator and the FPGA as the co-simulator platform for the digital hardware design. The work presented in this thesis consists of the creation of: A communication library in the host computer, a system in the FPGA that allows implementation of different digital designs with varying architectures, and an interface between the host computer and the FPGA to transmit the data. The efficiency of the proposed system is studied with the implementation of two common digital hardware designs, a PID controller and a filter. The results of the HIL simulations of those two hardware designs are used to verify the platform and measure the timing and area performance of the proposed HIL platform.

  • 23.
    Adam, Wettring
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, Faculty of Science & Engineering.
    Adaptive Filtering and Nonlinear Models for Post-processing of Weather Forecasts2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Kalman filters have been used by SMHI to improve the quality of their forecasts. Until now they have used a linear underlying model to do this. In this thesis it is investigated whether the performance can be improved by the use of nonlinear models such as polynomials and neural networks. The results suggest that an improvement is hard to achieve by this approach and that it is likely not worth the effort to implement a nonlinear model.

  • 24.
    Adén, Sebastian
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    Modellbaserad diagnostik tillämpad för hydrauliska applikationer2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [sv]

    I en globaliserad värld där produktägare finner sina produkter på alltmer avslägsna platser, ökar behovet av att på ett så ekonomiskt och tidseffektivt sätt som möjligt, utföra reperationer och underhållningsarbeten. Att erbjuda en stark och mer effektiv eftermarknadssupport kan öka företagens konkurrenskraft och framför allt göra dem kostnadseffektiva med avseende på lägre bemanningsstyrka. Ett sätt att underlätta underhållningsarbetet är genom att använda modellbaserad diagnos för att generera underlag vid exempelvis reperationsarbeten.

    Denna rapport undersöker möjligheterna att utifrån en modell av en hydraulisk applikation, utföra autogenererad diagnostik bland annat iform av felträdsanalys.

    Innehållet i rapporten beskriver även hur modelleringsarbetet har gått till och utveckling av modellens ingående komponenter.

    Examensarbetet är utfört på Combitech AB, Linköping. 

  • 25.
    Afsarinejad, Arash
    Linköping University, Department of Electrical Engineering.
    Synkronisering med SyncML2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    The last couple of years the use of mobile devices such as mobile phones and PDAs has increased tremendously. Most of the these devices have their own protocols for synchronising data and this has given rise to a need for a standard synchronisation protocol, SyncML. This thesis compares this protocol against the existing ones. The comparison shows that the preferred choice is SyncML.

    Also an application using SyncML has been developed. The application's task is to synchronise the calendar on a mobile phone with a database on a computer.

  • 26.
    Afzal, Nadeem
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Complexity and Power Reduction in Digital Delta-Sigma Modulators2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.

    In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.

    Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.

    A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.

    All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.

    List of papers
    1. Power efficient arrangement of oversampling sigma-delta DAC
    Open this publication in new window or tab >>Power efficient arrangement of oversampling sigma-delta DAC
    2012 (English)In: NORCHIP, 2012, IEEE , 2012, 1-4 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.

    Place, publisher, year, edition, pages
    IEEE, 2012
    Keyword
    digital-analogue conversion;sigma-delta modulation;DSDM;buss-split design;digital sigma-delta modulator;digital-to-analog conversion blocks;hardware efficient arrangement;oversampling sigma-delta DAC;power efficient arrangement;Complexity theory;Hardware;Modulation;Quantization;Sigma delta modulation;Signal to noise ratio;DAC complexity;Digital sigma-delta modulator;bit-split;composite architecture;modulator’s complexity;noise shaping
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112892 (URN)10.1109/NORCHP.2012.6403119 (DOI)978-1-4673-2221-8 (ISBN)978-1-4673-2222-5 (ISBN)
    Conference
    2012 NORCHIP, November 12-14, Copenhagen, Denmark
    Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2014-12-19Bibliographically approved
    2. Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
    Open this publication in new window or tab >>Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
    2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, 641-645 p.Article in journal (Refereed) Published
    Abstract [en]

    In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2014
    Keyword
    Delta-sigma (Delta Sigma); error-feedback multibit modulator; oversampling digital-to-analog converter
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-111264 (URN)10.1109/TCSII.2014.2331105 (DOI)000341985600001 ()
    Available from: 2014-10-15 Created: 2014-10-14 Last updated: 2017-12-05Bibliographically approved
    3. On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators
    Open this publication in new window or tab >>On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators
    2012 (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    In order to determine a maximum allowed input scale for the stable operation of higher-order delta-sigma modulators, the designers largely depend on the analytical and numerical analysis. In this brief, the maximum allowed input scale to a multi-bit digital error-feedback  deltasigma modulator of arbitrary order is derived, mathematically. The digital modulator with an arbitrary output word length is stable if its output does not overflow. Thus, to avoid overflow of the modulator output, the relations between the peak values of the involved digital signals are devised. A number of example configurations are presented to illustrate the usefulness of the derivations.

    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112895 (URN)
    Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2015-03-11Bibliographically approved
    4. Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
    Open this publication in new window or tab >>Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
    2012 (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.

    To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.

    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112896 (URN)
    Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2015-03-11Bibliographically approved
  • 27.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators2012Manuscript (preprint) (Other academic)
    Abstract [en]

    In order to determine a maximum allowed input scale for the stable operation of higher-order delta-sigma modulators, the designers largely depend on the analytical and numerical analysis. In this brief, the maximum allowed input scale to a multi-bit digital error-feedback  deltasigma modulator of arbitrary order is derived, mathematically. The digital modulator with an arbitrary output word length is stable if its output does not overflow. Thus, to avoid overflow of the modulator output, the relations between the peak values of the involved digital signals are devised. A number of example configurations are presented to illustrate the usefulness of the derivations.

  • 28.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Sadeghifar, Reza
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A study on power consumption of modified noise-shaper architectures for Sigma-Delta DACs2011In: Circuit Theory and Design (ECCTD), 2011, IEEE , 2011, 274-277 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.

  • 29.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power efficient arrangement of oversampling sigma-delta DAC2012In: NORCHIP, 2012, IEEE , 2012, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.

  • 30.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J. Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption2012Manuscript (preprint) (Other academic)
    Abstract [en]

    The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.

    To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.

  • 31.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Low-Complexity LMMSE Based Channel Estimation Algorithm for Multiple Standards in Mobile Terminals2010In: Proceedings of the Swedish System On Chip Conference, SSOCC 2010, 2010Conference paper (Other academic)
    Abstract [en]

    A less complex and generic channel estimation algorithm for long term evolution (LTE) and digital video broadcasting-handheld (DVB-H) downlink standards, is proposed. The technique, here referred to as minimum mean square error sliding window (MSW) technique, obtains less computational complexity than previous mean squared error (MSE) algorithms [3] at the cost of some 0.3 dB less SNR. The computational complexity is decreased by a factor 3 for the LTE 5-MHz downlink case and by 30 for the DVB-H standard case. Simulated results in terms of mean squared error and bit error rates are presented for a quadrature phase-shift keying (QPSK) systems with interleaving and coding of the data. All simulations are done at the behaviolar-level level.

  • 32.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Study of modified noise-shaper architectures for oversampled sigma-delta DACs2010In: NORCHIP, 2010, IEEE , 2010, 1-4 p.Conference paper (Other academic)
    Abstract [en]

    In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.

  • 33.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, 641-645 p.Article in journal (Refereed)
    Abstract [en]

    In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

  • 34.
    Agardt, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Löfgren, Markus
    Linköping University, Department of Electrical Engineering.
    Pilot Study of Systems to Drive Autonomous Vehicles on Test Tracks2008Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This Master’s thesis is a pilot study that investigates different systems to drive autonomous and non-autonomous vehicles simultaneously on test tracks. The thesis includes studies of communication, positioning, collision avoidance, and techniques for surveillance of vehicles which are suitable for implementation. The investigation results in a suggested system outline.

    Differential GPS combined with laser scanner vision is used for vehicle state estimation (position, heading, velocity, etc.). The state information is transmitted with IEEE 802.11 to all surrounding vehicles and surveillance center. With this information a Kalman prediction of the future position for all vehicles can be estimated and used for collision avoidance.

  • 35.
    Aghaee Ghaleshahi, Nima
    Linköping University, Department of Computer and Information Science. Linköping University, Faculty of Science & Engineering.
    Thermal Issues in Testing of Advanced Systems on Chip2015Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.

    Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.

    Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced.

    The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.

    All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.

  • 36.
    Aghaee Ghaleshahi, Nima
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs2015In: 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, Jan. 19-22, 2015., Institute of Electrical and Electronics Engineers (IEEE), 2015, 526-531 p.Conference paper (Refereed)
    Abstract [en]

    In a modern 3D IC, electrical connections between vertically stacked dies are made using through silicon vias. Through silicon vias are subject to undesirable early-life effects such as protrusion as well as void formation and growth. These effects result in opens, resistive opens, and stress induced carrier mobility reduction, and consequently circuit failures. Operating the ICs under extreme temperature cycling can effectively accelerate such early-life failures and make them detectable at the manufacturing test process. An integrated temperature-cycling acceleration and test technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration procedures. All these result in a reduction in the overall test costs. The proposed method is a schedule-based solution that creates the required temperature cycling effect along with performing the tests. Experimental results demonstrate its efficiency.

  • 37.
    Aghel Dawood, Menhel
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Obradovic, Dragan
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Guidelines for control equipment2013Independent thesis Basic level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [sv]

    Detta examensarbete är utfört på ABB LV System som är en del av företaget ABB i Sverige. Detta är ett företag som bygger kontrollutrustning till kunder som befinner sig i många delar av världen. Vår uppgift var att sätta samman en pärm med riktlinjer för montörerna.

    Pärmen ska vara lättläst och samtidigt innehålla alla standarder samt viktig fakta som kan behövas vid byggandet av kontrollutrustning.

    Riktlinjerna som framställts ledde till att montörerna blev bättre uppdaterade om de senaste riktlinjerna och standarder som leder idag. Tack vara att montörerna nu har allt samlat i en lättläslig pärm blir ledtiderna kortare.

  • 38.
    Aghighi, Meysam
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Computational Complexity of some Optimization Problems in Planning2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Automated planning is known to be computationally hard in the general case. Propositional planning is PSPACE-complete and first-order planning is undecidable. One method for analyzing the computational complexity of planning is to study restricted subsets of planning instances, with the aim of differentiating instances with varying complexity. We use this methodology for studying the computational complexity of planning. Finding new tractable (i.e. polynomial-time solvable) problems has been a particularly important goal for researchers in the area. The reason behind this is not only to differentiate between easy and hard planning instances, but also to use polynomial-time solvable instances in order to construct better heuristic functions and improve planners. We identify a new class of tractable cost-optimal planning instances by restricting the causal graph. We study the computational complexity of oversubscription planning (such as the net-benefit problem) under various restrictions and reveal strong connections with classical planning. Inspired by this, we present a method for compiling oversubscription planning problems into the ordinary plan existence problem. We further study the parameterized complexity of cost-optimal and net-benefit planning under the same restrictions and show that the choice of numeric domain for the action costs has a great impact on the parameterized complexity. We finally consider the parameterized complexity of certain problems related to partial-order planning. In some applications, less restricted plans than total-order plans are needed. Therefore, a partial-order plan is being used instead. When dealing with partial-order plans, one important question is how to achieve optimal partial order plans, i.e. having the highest degree of freedom according to some notion of flexibility. We study several optimization problems for partial-order plans, such as finding a minimum deordering or reordering, and finding the minimum parallel execution length.

    List of papers
    1. Oversubscription planning: Complexity and compilability
    Open this publication in new window or tab >>Oversubscription planning: Complexity and compilability
    2014 (English)In: Proceedings of the Twenty-Eighth AAAI Conference on Artificial Intelligence, AI Access Foundation , 2014, Vol. 3, 2221-2227 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    Many real-world planning problems are oversubscription problems where all goals are not simultaneously achievable and the planner needs to find a feasible subset. We present complexity results for the so-called partial satisfaction and net benefit problems under various restrictions; this extends previous work by van den Briel et al. Our results reveal strong connections between these problems and with classical planning. We also present a method for efficiently compiling oversubscription problems into the ordinary plan existence problem; this can be viewed as a continuation of earlier work by Keyder and Geffner.

    Place, publisher, year, edition, pages
    AI Access Foundation, 2014
    National Category
    Computer and Information Science
    Identifiers
    urn:nbn:se:liu:diva-116727 (URN)2-s2.0-84908192348 (Scopus ID)9781577356790 (ISBN)
    Conference
    28th AAAI Conference on Artificial Intelligence, AAAI 2014, 26th Innovative Applications of Artificial Intelligence Conference, IAAI 2014 and the 5th Symposium on Educational Advances in Artificial Intelligence, EAAI 2014
    Available from: 2015-04-09 Created: 2015-04-02 Last updated: 2017-05-17
    2. Tractable Cost-Optimal Planning over Restricted Polytree Causal Graphs
    Open this publication in new window or tab >>Tractable Cost-Optimal Planning over Restricted Polytree Causal Graphs
    2015 (English)In: Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, AAAI Press, 2015Conference paper, Published paper (Refereed)
    Abstract [en]

    Causal graphs are widely used to analyze the complexity of planning problems. Many tractable classes have been identified with their aid and state-of-the-art heuristics have been derived by exploiting such classes. In particular, Katz and Keyder have studied causal graphs that are hourglasses (which is a generalization of forks and inverted-forks) and shown that the corresponding cost-optimal planning problem is tractable under certain restrictions. We continue this work by studying polytrees (which is a generalization of hourglasses) under similar restrictions. We prove tractability of cost-optimal planning by providing an algorithm based on a novel notion of variable isomorphism. Our algorithm also sheds light on the k-consistency procedure for identifying unsolvable planning instances. We speculate that this may, at least partially, explain why merge-and-shrink heuristics have been successful for recognizing unsolvable instances.

    Place, publisher, year, edition, pages
    AAAI Press, 2015
    Series
    Proceedings of the AAAI Conference on Artificial Intelligence, ISSN 2159-5399, E-ISSN 2374-3468
    Keyword
    automated planning, causal graph, polynomial-time algorithm, cost-optimal planning, polytree
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:liu:diva-118729 (URN)978-1-57735-703-2 (ISBN)
    Conference
    29th AAAI Conference on Artificial Intelligence (AAAI-15), January 25–30, Austin, TX, USA
    Funder
    CUGS (National Graduate School in Computer Science)
    Available from: 2015-06-03 Created: 2015-06-03 Last updated: 2017-05-17
    3. Cost-optimal and Net-benefit Planning--A Parameterised Complexity View
    Open this publication in new window or tab >>Cost-optimal and Net-benefit Planning--A Parameterised Complexity View
    2015 (English)In: 24th International Joint Conference on Artificial Intelligence (IJCAI-15), 2015Conference paper, Published paper (Refereed)
    Abstract [en]

    Cost-optimal planning (COP) uses action costs and asks for a minimum-cost plan. It is sometimes assumed that there is no harm in using actions with zero cost or rational cost. Classical complexity analysis does not contradict this assumption; planning is PSPACE-complete regardless of whether action costs are positive or non-negative, integer or rational. We thus apply parameterised complexity analysis to shed more light on this issue. Our main results are the following. COP is W[2]-complete for positive integer costs, i.e. it is no harder than finding a minimum-length plan, but it is para-NPhard if the costs are non-negative integers or positive rationals. This is a very strong indication that the latter cases are substantially harder. Net-benefit planning (NBP) additionally assigns goal utilities and asks for a plan with maximum difference between its utility and its cost. NBP is para-NP-hard even when action costs and utilities are positive integers, suggesting that it is harder than COP. In addition, we also analyse a large number of subclasses, using both the PUBS restrictions and restricting the number of preconditions and effects.

    National Category
    Transport Systems and Logistics
    Identifiers
    urn:nbn:se:liu:diva-128181 (URN)9781577357384 (ISBN)
    Conference
    24th International Joint Conference on Artificial Intelligence (IJCAI-15)
    Funder
    CUGS (National Graduate School in Computer Science), 1054Swedish Research Council, 621- 2014-4086
    Available from: 2016-05-20 Created: 2016-05-20 Last updated: 2017-10-06Bibliographically approved
    4. A Multi-parameter Complexity Analysis of Cost-optimal and Net-benefit Planning
    Open this publication in new window or tab >>A Multi-parameter Complexity Analysis of Cost-optimal and Net-benefit Planning
    2016 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    Aghighi and Bäckström have previously studied cost-optimal planning (COP) and net-benefit planning (NBP) for three action cost domains: the positive integers (Z_+), the non-negative integers (Z_0) and the positive rationals (Q_+). These were indistinguishable under standard complexity analysis for both problems, but separated for COP using parameterised complexity analysis. With the plan cost, k, as parameter, COP was W[2]-complete for Z_+, but para-NP-hard for both Z_0 and Q_+, i.e. presumably much harder. NBP was para-NP-hard for all three domains, thus remaining unseparable. We continue by considering combinations with several additional parameters and also the non-negative rationals (Q_0). Examples of new parameters are the plan length, l, and the largest denominator of the action costs, d. Our findings include: (1) COP remains W[2]-hard for all domains, even if combining all parameters; (2) COP for Z_0 is in W[2] for the combined parameter {k,l}; (3) COP for Q_+ is in W[2] for {k,d} and (4) COP for Q_0 is in W[2] for {k,d,l}. For NBP we consider further additional parameters, where the most crucial one for reducing complexity is the sum of variable utilities. Our results help to understand the previous results, eg. the separation between Z_+ and Q_+ for COP, and to refine the previous connections with empirical findings.

    Place, publisher, year, edition, pages
    AAAI Press, 2016
    Keyword
    cost-optimal planning, parameterised complexity, numeric domains
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:liu:diva-136278 (URN)9781577357575 (ISBN)
    Conference
    Twenty-Sixth International Conference on Automated Planning and Scheduling (ICAPS-16)
    Available from: 2017-04-05 Created: 2017-04-05 Last updated: 2017-10-06
    5. Plan Reordering and Parallel Execution -- A Parameterized Complexity View
    Open this publication in new window or tab >>Plan Reordering and Parallel Execution -- A Parameterized Complexity View
    2017 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    Bäckström has previously studied a number of optimization problems for partial-order plans, like finding a minimum deordering (MCD) or reordering (MCR), and finding the minimum parallel execution length (PPL), which are all NP-complete. We revisit these problems, but applying parameterized complexity analysis rather than standard complexity analysis. We consider various parameters, including both the original and desired size of the plan order, as well as its width and height. Our findings include that MCD and MCR are W[2]-hard and in W[P] when parameterized with the desired order size, and MCD is fixed-parameter tractable (fpt) when parameterized with the original order size. Problem PPL is fpt if parameterized with the size of the non-concurrency relation, but para-NP-hard in most other cases. We also consider this problem when the number (k) of agents, or processors, is restricted, finding that this number is a crucial parameter; this problem is fixed-parameter tractable with the order size, the parallel execution length and k as parameter, but para-NP-hard without k as parameter.

    Place, publisher, year, edition, pages
    AAAI Press, 2017
    Keyword
    Partially ordered plan, Parameterized complexity, Complexity of planning, Plan reordering, Parallel plan execution
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:liu:diva-136279 (URN)
    Conference
    Thirty-First AAAI Conference on Artificial Intelligence (AAAI-17)
    Available from: 2017-04-05 Created: 2017-04-05 Last updated: 2017-05-17Bibliographically approved
  • 39.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    A Multi-parameter Complexity Analysis of Cost-optimal and Net-benefit Planning2016Conference paper (Refereed)
    Abstract [en]

    Aghighi and Bäckström have previously studied cost-optimal planning (COP) and net-benefit planning (NBP) for three action cost domains: the positive integers (Z_+), the non-negative integers (Z_0) and the positive rationals (Q_+). These were indistinguishable under standard complexity analysis for both problems, but separated for COP using parameterised complexity analysis. With the plan cost, k, as parameter, COP was W[2]-complete for Z_+, but para-NP-hard for both Z_0 and Q_+, i.e. presumably much harder. NBP was para-NP-hard for all three domains, thus remaining unseparable. We continue by considering combinations with several additional parameters and also the non-negative rationals (Q_0). Examples of new parameters are the plan length, l, and the largest denominator of the action costs, d. Our findings include: (1) COP remains W[2]-hard for all domains, even if combining all parameters; (2) COP for Z_0 is in W[2] for the combined parameter {k,l}; (3) COP for Q_+ is in W[2] for {k,d} and (4) COP for Q_0 is in W[2] for {k,d,l}. For NBP we consider further additional parameters, where the most crucial one for reducing complexity is the sum of variable utilities. Our results help to understand the previous results, eg. the separation between Z_+ and Q_+ for COP, and to refine the previous connections with empirical findings.

  • 40.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bäckström, Christer
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Plan Reordering and Parallel Execution -- A Parameterized Complexity View2017Conference paper (Refereed)
    Abstract [en]

    Bäckström has previously studied a number of optimization problems for partial-order plans, like finding a minimum deordering (MCD) or reordering (MCR), and finding the minimum parallel execution length (PPL), which are all NP-complete. We revisit these problems, but applying parameterized complexity analysis rather than standard complexity analysis. We consider various parameters, including both the original and desired size of the plan order, as well as its width and height. Our findings include that MCD and MCR are W[2]-hard and in W[P] when parameterized with the desired order size, and MCD is fixed-parameter tractable (fpt) when parameterized with the original order size. Problem PPL is fpt if parameterized with the size of the non-concurrency relation, but para-NP-hard in most other cases. We also consider this problem when the number (k) of agents, or processors, is restricted, finding that this number is a crucial parameter; this problem is fixed-parameter tractable with the order size, the parallel execution length and k as parameter, but para-NP-hard without k as parameter.

  • 41.
    Aghighi, Meysam
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jonsson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ståhlberg, Simon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Tractable Cost-Optimal Planning over Restricted Polytree Causal Graphs2015In: Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence, AAAI Press, 2015Conference paper (Refereed)
    Abstract [en]

    Causal graphs are widely used to analyze the complexity of planning problems. Many tractable classes have been identified with their aid and state-of-the-art heuristics have been derived by exploiting such classes. In particular, Katz and Keyder have studied causal graphs that are hourglasses (which is a generalization of forks and inverted-forks) and shown that the corresponding cost-optimal planning problem is tractable under certain restrictions. We continue this work by studying polytrees (which is a generalization of hourglasses) under similar restrictions. We prove tractability of cost-optimal planning by providing an algorithm based on a novel notion of variable isomorphism. Our algorithm also sheds light on the k-consistency procedure for identifying unsolvable planning instances. We speculate that this may, at least partially, explain why merge-and-shrink heuristics have been successful for recognizing unsolvable instances.

  • 42.
    Ahani, Ghafour
    et al.
    Komar University of Science and Technology, Iraq.
    Yuan, Di
    Linköping University, Department of Science and Technology, Communications and Transport Systems. Linköping University, Faculty of Science & Engineering.
    Ding, Wei
    Ranplan Wireless Network Design Ltd, England.
    On SC-FDMA Resource Allocation with Power Control2016In: 2016 IEEE 21ST INTERNATIONAL WORKSHOP ON COMPUTER AIDED MODELLING AND DESIGN OF COMMUNICATION LINKS AND NETWORKS (CAMAD), IEEE , 2016, 112-116 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, single-carrier frequency division multiple accesses (SC-FDMA) is discussed. In particular, minimum stun power, subject to meeting users demand is considered. There are two channel allocation schemes, localized and interleaved. In localized scheme, a block of convective channels in the spectrum is allocated to each user. In interleaved scheme, channels will be spread out over the spectrum and will be distributed equidistantly. It has been previously assumed that when a block of channels is assigned to a user, the same amount of power will be allocated to each channel. However, the power could be used more efficiently without this assumption We show that the resulting power allocation problem can be solved in linear time and propose an optimal power allocation procedure. Next, the effect of this new power optimization procedure is investigated numerically. In the next part of paper, we prove that for the interleaved scheme, Minimum sum power problem with or without this new power optimization is polynomial solvable. Finally, we numerically compare localized and interleaved SC-FDMA with and without power optimization The results show that the localized scheme with the new power optimization yields the best performance

  • 43.
    Ahlberg, Jesper
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Blomquist, Esbjörn
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Online Identification of Running Resistance and Available Adhesion of Trains2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Two important physical aspects that determine the performance of a running train are the total running resistance that acts on the whole train moving forward, and the available adhesion (utilizable wheel-rail-friction) for propulsion and breaking. Using the measured and available signals, online identification of the current running resistance and available adhesion and also prediction of future values for a distance ahead of the train, is desired. With the aim to enhance the precision of those calculations, this thesis investigates the potential of online identification and prediction utilizing the Extended Kalman Filter.

    The conclusions are that problems with observability and sensitivity arise, which result in a need for sophisticated methods to numerically derive the acceleration from the velocity signal. The smoothing spline approximation is shown to provide the best results for this numerical differentiation. Sensitivity and its need for high accuracy, especially in the acceleration signal, results in a demand of higher sample frequency. A desire for other profound ways of collecting further information, or to enhance the models, arises with possibilities of future work in the field.

  • 44.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering, Image Coding. Linköping University, The Institute of Technology.
    An active model for facial feature tracking2002In: EURASTP journal an applied signal processing, ISSN 1110-8657, E-ISSN 1687-0433, Vol. 2002, no 6, 566-571 p.Article in journal (Refereed)
    Abstract [en]

    We present a system for finding and tracking a face and extract global and local animation parameters from a video sequence. The system uses an initial colour processing step for finding a rough estimate of the position, size, and inplane rotation of the face, followed by a refinement step drived by an active model. The latter step refines the previous estimate, and also extracts local animation parameters. The system is able to track the face and some facial features in near real-time, and can compress the result to a bitstream compliant to MPEG-4 face and body animation.

  • 45.
    Ahlberg, Jörgen
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, Faculty of Science & Engineering. FOI, SE-58111 Linkoping, Sweden.
    Optimizing Object, Atmosphere, and Sensor Parameters in Thermal Hyperspectral Imagery2017In: IEEE Transactions on Geoscience and Remote Sensing, ISSN 0196-2892, E-ISSN 1558-0644, Vol. 55, no 2, 658-670 p.Article in journal (Refereed)
    Abstract [en]

    We address the problem of estimating atmosphere parameters (temperature and water vapor content) from data captured by an airborne thermal hyperspectral imager and propose a method based on linear and nonlinear optimization. The method is used for the estimation of the parameters (temperature and emissivity) of the observed object as well as sensor gain under certain restrictions. The method is analyzed with respect to sensitivity to noise and the number of spectral bands. Simulations with synthetic signatures are performed to validate the analysis, showing that the estimation can be performed with as few as 10-20 spectral bands at moderate noise levels. The proposed method is also extended to exploit additional knowledge, for example, measurements of atmospheric parameters and sensor noise. Additionally, we show how to extend the method in order to improve spectral calibration.

  • 46.
    Ahlberg, Jörgen
    et al.
    Swedish Defence Research Agency, Sweden.
    Folkesson, Martin
    Swedish Defence Research Agency, Sweden.
    Grönwall, Christina
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Horney, Tobias
    Swedish Defence Research Agency, Sweden.
    Jungert, Erland
    Swedish Defence Research Agency, Sweden.
    Klasén, Lena
    Swedish Defence Research Agency, Sweden.
    Ulvklo, Morgan
    Swedish Defence Research Agency, Sweden.
    Ground Target Recognition in a Query-Based Multi-Sensor Information System2006Report (Other academic)
    Abstract [en]

    We present a system covering the complete process for automatic ground target recognition, from sensor data to the user interface, i.e., from low level image processing to high level situation analysis. The system is based on a query language and a query processor, and includes target detection, target recognition, data fusion, presentation and situation analysis. This paper focuses on target recognition and its interaction with the query processor. The target recognitionis executed in sensor nodes, each containing a sensor and the corresponding signal/image processing algorithms. New sensors and algorithms are easily added to the system. The processing of sensor data is performed in two steps; attribute estimation and matching. First, several attributes, like orientation and dimensions, are estimated from the (unknown but detected) targets. These estimates are used to select the models of interest in a matching step, where the targetis matched with a number of target models. Several methods and sensor data types are used in both steps, and data is fused after each step. Experiments have been performed using sensor data from laser radar, thermal and visual cameras. Promising results are reported, demonstrating the capabilities of the target recognition algorithms, the advantages of the two-level data fusion and the query-based system.

  • 47.
    Ahlberg, Jörgen
    et al.
    Division of Information Systems, Swedish Defence Research Agency (FOI), Linköping, Sweden.
    Pandzic, Igor
    Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia.
    Facial Action Tracking2011In: Handbook of Face Recognition / [ed] Stan Z. Li, Anil K. Jain, London: Springer London, 2011, 2, 461-486 p.Chapter in book (Refereed)
    Abstract [en]

    This chapter explains the basics of parametric face models used for face and facial action tracking as well as fundamental strategies and methodologies for tracking. A few tracking algorithms serving as pedagogical examples are described in more detail.

  • 48.
    Ahlberg, Sven
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Evaluation of Different Radio-Based Indoor Positioning Methods2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Today, positioning with GPS and the advantages this entails are almost infinitive, which means that the technology can be utilized in a variety of applications. Unfortunately, there exists a lot of limitations in conjunction with the signals from the GPS can’t reach inside e.g. buildings or underground. This means that an alternative solution that works indoors needs to be developed.

    The report presents the four most common radio-based technologies, Bluetooth,Wi-Fi, UWB and RFID, which can be used to determine a position. These all have different advantages in cost, accuracy and latency, which means that there exist a number of different applications.

    The radio-based methods use the measurement techniques, RSSI, TOA, TDOA, Cell-ID, PD or AOA to gather data. The choice of measurement technique is mainly dependent of which radio-based method being used, since their accuracy depends on the quality of the measurements and the size of the detection area, which means that all measurement techniques have different advantages and disadvantages.

    The measurement data is processed with one of the positioning methods, LS, NLS, ML, Cell-ID, WC or FP, to estimate a position. The choice of positioning method also depends on the quality of the measurements in combination with the size of the detection area.

    To evaluate the different radio-based methods together with measurement techniques and positioning methods, accuracy, latency and cost are being compared. This is used as the basis for the choice of positioning method, since a general solution can get summarized by finding the least expensive approach which can estimate an unknown position with sufficiently high accuracy.

  • 49.
    Ahlgren, Simon
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Aini, Daniel
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Conversion and Analysis of Telemetric Data from the CCSDS Standard2017Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    When communicating with spacecrafts, the international standard is to use the protocols defined by CCSDS. In this study, the Space Packet Protocol from CCSDS is converted to the Digital Recording Standard used in aviation. The goal of the study is to find out in what way such a conversion can be made, as well as analyzing the efficiency of different packing methods for the Digital Recording Standard. An application is developed in order to perform the conversion, and the performance of said application is profiled using different packet sizes. In the end the results are evaluated and an optimal packet size is found in terms of runtime and memory usage. In the end we conclude that a packet size of 216 bytes is best when prioritizing speed, and a packet size of 219 bytes is best when prioritizing memory.

  • 50.
    Ahlin, Karl
    Linköping University, Department of Electrical Engineering.
    Quality of Service i IP-nätverk2003Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    The original promise behind the Internet Protocol was to deliver data from a sender to the receiver using a best-effort approach. This means that the protocol makes no guarantees except that it will try to deliver the data to the destination. If some problem occurs the packet may be discarded by the network without any notice. No guarantees are made regarding the time it takes to deliver the data, the rate at which data will be delivered or if data is delivered in the same order it was sent. The best-effort approach is arguably the reason behind the success of the Internet Protocol and is what makes IP scalable to networks the size of the Internet. However, this approach is also a problem for network operators who want to offer better quality of service to some of their customers. This master thesis will discuss some of the theories behind the implementation of quality of service schemes in an IP network and also provide an example of how to implement it in an existing network.

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