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  • 1.
    Aasa, Amanda
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Svennblad, Amanda
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Design of an Automated Test Setup for Power-Controlled Nerve Stimulator Using NFC for Implantable Sensors2021Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Electrical stimulation on nerves is a relatively new area of research and has been proved to speed up recoveryfrom nerve damage. In this work, the efficiency and stability of antennas integrated on printed circuit boards provided by the department of electrical engineering are examined. An automated test bench containing a stepmotor with a slider and an Arduino is created. Different setups were used when measuring on the boards, which resulted in that the largest antenna gave the most stable output despite the distance between transmitterand receiver. The conclusion was that the second best antenna and the smallest one would be suitable as well,and the better choice if it is to be implemented under the skin. A physical setup consisting of LEDs, an Arduino, a computer, and a function generator was created to examinethe voltage control functionality, where colored LEDs were lit depending on the voltage level. The functionality was then implemented in a circuit that in the future shall be integrated on the printed circuit board. To control high voltages a limiter circuit was examined and implemented. The circuit was simulated and tested, with a realization that a feature covering voltage enlargement is needed for the future. 

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  • 2.
    Alexandersson, Johan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Nordin, Olle
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Implementation of CAN Communication Stack in AUTOSAR2015Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    In the automotive industry today, embedded systems have reached a level of complexity which is not maintainable with the traditional approach of design- ing automotive embedded systems. For this purpose, many of the worlds leading automotive manufacturers have formed an alliance to apprehend this problem. This has resulted in AUTOSAR, an open standardized architecture for automotive embedded systems, which strives for increased flexibility and safety regulations. This thesis will explore the possibilities of implementing a CAN Communication stack using the AUTOSAR architecture and its corresponding methodology. As a result of this thesis, a complete AUTOSAR CAN communication stack has been implemented, as well has a simulator application with the purpose of testing its functionality. 

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  • 3.
    Andersson, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Olsson, Christian
    Linköping University, Department of Electrical Engineering, Electronics System.
    Linearization of Power Amplifier using Digital Predistortion, Implementation on FPGA2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The purpose of this thesis is to linearize a power amplifier using digital predistortion. A power amplifier is a nonlinear system, meaning that when fed with a pure input signal the output will be distorted. The idea behind digital predistortion is to distort the signal before feeding it to the power amplifier. The combined distortions from the predistorter and the power amplifier will then ideally cancel each other. In this thesis, two different approaches are investigated and implemented on an FPGA. The first approach uses a nonlinear model that tries to cancel out the nonlinearities of the power amplifier. The second approach is model-free and instead makes use of a look-up table that maps the input to a distorted output. Both approaches are made adaptive so that the parameters are continuously updated using adaptive algorithms. First the two approaches are simulated and tested thoroughly with different parameters and with a power amplifier model extracted from the real amplifier. The results are shown satisfactory in the simulations, giving good linearization for both the model and the model-free technique. The two techniques are then implemented on an FPGA and tested on the power amplifier. Even though the results are not as well as in the simulations, the system gets more linear for both the approaches. The results vary widely due to different circumstances such as input frequency and power. Typically, the distortions can be attenuated with around 10 dB. When comparing the two techniques with each other, the model-free method shows slightly better results.

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  • 4.
    Andersson, Isak
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Karlsson, Melki
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Body Coupled Communication: Ändring av prototypkort2014Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Communication using the human body as a transmission medium, the capacitive coupling between the skin and sensor, has been an active research area for PAN (Personal Area Network) since Thomas Guthrie Zimmerman introduced the technique in 1995. The reason for this is to examine the benefits and uses of a communication method that does not emit RF signals and thus reduce the risk of unauthorized interception.

    This report describes a thesis that examines the possibility of elimination of USB to UART converter on Microchip BodyCom through software USB-stack and combine this with Body Coupled Communication functionality in a single microcontroller. Furthermore, studies on if the application code in Body Coupled Communication transmitters can be modified to extend functionality.

    It was given in the conditions that microcontrollers from Microchip should be used, furthermore, low price and low power consumption were important, especially for the transmitter. The method for achieving this has been the use of Microchip BodyCom development kit with USB Microchip low pin count development kit and Microchip USB firmware framework.

    The result was that the USB- to UART-converter could be integrated with Microchip BodyCom, using software USB-stack and a modified program code for BodyCom in a single microcontroller.

    Only your imagination sets the limits for Body Coupled Communication can be used for. For example, it would be possible to exchange electronic business cards by a handshake or open a locked door only by using the handle.

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  • 5.
    Athalye, Akshay
    et al.
    Stony Brook University, USA.
    Savic, Vladimir
    Technical University of Madrid, Spain.
    Bolic, Miodrag
    University of Ottawa, Canada.
    Djuric, Petar M.
    Stony Brook University, USA.
    A Radio Frequency Identification System for accurate indoor localization2011In: Proc. of IEEE Intl. Conf. on Acoustics, Speech and Signal Processing (ICASSP), 2011, p. 1777-1780Conference paper (Refereed)
    Abstract [en]

    In this paper we present a novel Radio Frequency Identification (RFID) system for accurate indoor localization. The system is composed of a standard Ultra High Frequency (UHF), ISO-18006C compliant RFID reader, a large set of standard passive RFID tags whose locations are known, and a newly developed tag-like RFID component that is attached to the items that need to be localized. The new semi-passive component, referred to as sensatag (sense-a-tag), has a dual functionality wherein it can sense the communication between the reader and standard tags which are in its proximity, and also communicate with the reader like standard tags using backscatter modulation. Based on the information conveyed by the sensatags to the reader, localization algorithms based on binary sensor principles can be developed. We present results from real measurements that show the accuracy of the proposed system.

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  • 6.
    Athalye, Akshay
    et al.
    Stony Brook University, USA.
    Savic, Vladimir
    Signal Processing Application Group, Universidad Politecnica de Madrid, Madrid, Spain.
    Bolic, Miodrag
    University of Ottawa, Canada.
    Djuric, Petar M.
    Stony Brook University, USA.
    Novel Semi-Passive RFID System for Indoor Localization2013In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 13, no 2, p. 528-537Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a novel semi-passive radio-frequency identification (RFID) system for accurate indoor localization. The system is composed of a standard ultra high frequency (UHF) ISO-18000-6C compliant RFID reader, a set of standard passive RFID tags whose locations are known, and a newly developed tag-like RFID component, which is attached to the items that need to be localized. The new semi-passive component, referred to as sensatag (sense-a-tag), has a dual functionality: it can sense and decode communication between the reader and standard tags in its proximity, and can communicate with the reader like standard tags using backscatter modulation. Based on the information conveyed by the sensatags to the reader, localization algorithms based on binary sensor principles can be developed. We conduct a number of experiments in a laboratory to quantify the performance of our system, including two real applications, one finding the exact placement of items on shelves, and the other estimating the direction of item movement.

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  • 7.
    Axelsson, Jakob
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Analysis and Synthesis of Heterogeneous Real-Time Systems1997Doctoral thesis, monograph (Other academic)
    Abstract [en]

    During the development of a real-time system the main goal is to find an implementation that satisfies the specified timing constraints. Often, it is most cost-effective to use a heterogeneous solution based on a mixture of different microprocessors and application-specific integrated circuits. There is however a lack of techniques to handle the development of heterogeneously implemented systems, and this thesis therefore presents a novel approach inspired by research in the area of hardware/software codesign. The behaviour of the entire system is specified in a high-level, homogeneous description, independently of how different parts will later be implemented, and a thorough design space exploration is performed at the system level using automatic or semi-automatic synthesis tools which operate on virtual prototypes of the implementation.

    The objective of the synthesis is to find the least costly implementation which meets all timing constraints, and in order to predict these characteristics of the final system, different analysis methods are needed. The thesis presents an intrinsic analysis which estimates the hardware resource usage of individual tasks, and an extrinsic analysis for determining the effects of resource sharing between several concurrent tasks. The latter is similar to the fixed-priority schedulability analysis used for single-processor systems, but extended to heterogeneous architectures. Since these analysis procedures are applied early in the design process, there are always some discrepancies between the estimated data and the actual characteristics of the final system, and constructive ways of dealing with these inaccuracies are therefore also presented.

    Several synthesis algorithms are proposed for different aspects of the design. The hardware architecture is assembled from a component library using heuristic search techniques, and three alternative algorithms are evaluated in the thesis. The optimal partitioning of the functionality on an architecture is found using a branch-and-bound algorithm. Finally, a fixed-priority scheduler is instantiated by assigning priorities to the concurrent tasks of the behaviour. Together, the proposed analysis and synthesis methods provide a solid basis for systematic engineering of heterogeneous real-time systems.

  • 8.
    Baek, Iljoo
    et al.
    Carnegie Mellon Univ, PA 15213 USA.
    Chen, Wei
    Purdue Univ, IN 47907 USA.
    Zhu, Zhihao
    Carnegie Mellon Univ, PA 15213 USA.
    Samii, Soheil
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Rajkumar, Ragunathan Raj
    Carnegie Mellon Univ, PA 15213 USA.
    FT-DeepNets: Fault-Tolerant Convolutional Neural Networks with Kernel-based Duplication2022In: 2022 IEEE WINTER CONFERENCE ON APPLICATIONS OF COMPUTER VISION (WACV 2022), IEEE COMPUTER SOC , 2022, p. 1878-1887Conference paper (Refereed)
    Abstract [en]

    Deep neural network (deepnet) applications play a crucial role in safety-critical systems such as autonomous vehicles (AVs). An AV must drive safely towards its destination, avoiding obstacles, and respond quickly when the vehicle must stop. Any transient errors in software calculations or hardware memory in these deepnet applications can potentially lead to dramatically incorrect results. Therefore, assessing and mitigating any transient errors and providing robust results are important for safety-critical systems. Previous research on this subject focused on detecting errors and then recovering from the errors by re-running the network. Other approaches were based on the extent of full network duplication such as the ensemble learning-based approach to boost system fault-tolerance by leveraging each models advantages. However, it is hard to detect errors in a deep neural network, and the computational overhead of full redundancy can be substantial. We first study the impact of the error types and locations in deepnets. We next focus on selecting which part should be duplicated using multiple ranking methods to measure the order of importance among neurons. We find that the duplication overhead for computation and memory is a tradeoff between algorithmic performance and robustness. To achieve higher robustness with less system overhead, we present two error protection mechanisms that only duplicate parts of the network from critical neurons. Finally, we substantiate the practical feasibility of our approach and evaluate the improvement in the accuracy of a deepnet in the presence of errors. We demonstrate these results using a case study with real-world applications on an Nvidia GeForce RTX 2070Ti GPU and an Nvidia Xavier embedded platform used by automotive OEMs.

  • 9. Order onlineBuy this publication >>
    Bengtsson, Tomas
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Testing and Logic Optimization Techniques for Systems on Chip2012Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Today it is possible to integrate more than one billion transistors onto a single chip. This has enabled implementation of complex functionality in hand held gadgets, but handling such complexity is far from trivial. The challenges of handling this complexity are mostly related to the design and testing of the digital components of these chips.

    A number of well-researched disciplines must be employed in the efficient design of large and complex chips. These include utilization of several abstraction levels, design of appropriate architectures, several different classes of optimization methods, and development of testing techniques. This thesis contributes mainly to the areas of design optimization and testing methods.

    In the area of testing this thesis contributes methods for testing of on-chip links connecting different clock domains. This includes testing for defects that introduce unacceptable delay, lead to excessive crosstalk and cause glitches, which can produce errors. We show how pure digital components can be used to detect such defects and how the tests can be scheduled efficiently.

    To manage increasing test complexity, another contribution proposes to raise theabstraction level of fault models from logic level to system level. A set of system level faultmodels for a NoC-switch is proposed and evaluated to demonstrate their potential.

    In the area of design optimization, this thesis focuses primarily on logic optimization. Two contributions for Boolean decomposition are presented. The first one is a fast heuristic algorithm that finds non-disjoint decompositions for Boolean functions. This algorithm operates on a Binary Decision Diagram. The other contribution is a fast algorithm for detecting whether a function is likely to benefit from optimization for architectures with a gate depth of three with an XOR-gate as the third gate.

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    Testing and Logic Optimization Techniques for Systems on Chip
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    omslag
  • 10.
    Bengtz, Gustaf
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Analysis of new and alternative encryption algorithms and scrambling methods for digital-tv and implementation of a new scrambling algorithm (AES128) on FPGA.2014Independent thesis Advanced level (degree of Master (Two Years)), 300 HE creditsStudent thesis
    Abstract [en]

    This report adresses why the currently used scrambling standard CSA needs a replacement. Proposed replacements to CSA are analyzed to some extent, and an alternative replacement (AES128) is analyzed.

    One alternative being the CSA3, and the other being the CISSA algorithm. Both of the proposed algorithms use the AES algorithm as a base. The CSA3 combines AES128 with a secret cipher, the XRC, while CISSA uses the AES cipher in a feedback mode. The different utilizations makes CSA3 hardware friendly and CISSA software friendly.

    The implementation of the Advanced Encryption Standard (AES) is analyzed for a 128 bit key length based design, and a specific implementation is presented.

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    csa3_scrambling_report
  • 11.
    Bläser, Arvid
    Linköping University, Department of Science and Technology, Physics, Electronics and Mathematics. Linköping University, Faculty of Science & Engineering.
    Application demonstrator for green IoT unit including Ligna S-power2022Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Ligna Energy has developed a printable battery, called S-Power. It is based on research in organic electronics. In order to demonstrate the functionality of the new batteries, an IoT device was developed. The demonstrator consisted of a Sensor for temperature and relative humidity (RH), LoRWAN communication and a circuit for energy harvesting. Photovoltaic cells from Epishine were used in order to be able to harvest energy in low light conditions. At an illuminance of 200 lux, the demonstrator was able to sample the temperature and RH and send it by radio communication every two minutes. If no light at all is available, the demonstrator can sample data and send it every 30 minutes for over 12 hours.

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  • 12.
    Blåberg, Anton
    et al.
    Linköping University, Department of Computer and Information Science, Human-Centered systems.
    Lindahl, Gustav
    Linköping University, Department of Computer and Information Science, Human-Centered systems.
    Empirical Data Based Predictive Warning System on an Automated Guided Vehicle2022Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    An Automated Guided Vehicle (AGV) must follow protective regulations to avoidcrashing into people when autonomously driving in industries. These safety norms require AGVs to enable protective fields, which perform hard braking when objects enter aspecific area in front of the vehicle. Warning fields, or warning systems, are similar fieldsthat decrease the speed of the AGV before objects enter the protective fields to enable asteadier driving. Today at Toyota Material Handling Manufacturing Sweden (TMHMS),warning systems have been implemented but the systems are too sensitive to objects outside of the AGVs path.The purpose of this thesis is to develop a predictive warning system based on empiricaldata from previous driving scenarios. By storing previous positions, the warning systemcould estimate a trajectory based on simple statistics and deploy speed limiting decisionsif objects appear in the upcoming predicted path.The predictive warning system was compared to the current warning system and adeactivated warning system setup in driving performance and driving dynamics. Performance was measured by measuring time to finish an industry-like test track and dynamicswas subjectively rated from a group of experienced AGV developers from TMHMS. Results showed that a predictive warning system drove the test track faster and with betterdynamics than the current warning system and the no warning system setup.Key findings are that a predictive warning system based on empirical data performedbetter in most cases but has some extra requirements to function. Firstly, the method require the AGV to mostly drive on previously driven paths to produce good results. Secondly the warning system requires a somewhat powerful on board computer to handlethe computations. Finally, the warning system requires spatial awareness of pose for thevehicle, as well as structure and shape for deployed protective fields.

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    Empirical_Data_Based_Predictive_Warning_System_on_an_Automated_Guided_Vehicle
  • 13.
    Boudjadar, Abdeldjalil
    et al.
    Computer Science, Aalborg University, Denmark.
    David, Alexandre
    Computer Science, Aalborg University, Denmark.
    Hyun Kim, Jin
    Computer Science, Aalborg University, Denmark.
    Larsen, Kim G.
    Computer Science, Aalborg University, Denmark.
    Mikučionis, Marius
    Computer Science, Aalborg University, Denmark.
    Nyman, Ulrik
    Computer Science, Aalborg University, Denmark.
    Skou, Arne
    Computer Science, Aalborg University, Denmark.
    Statistical and exact schedulability analysis of hierarchical scheduling systems2016In: Science of Computer Programming, ISSN 0167-6423, E-ISSN 1872-7964, Vol. 127, p. 103-130Article in journal (Refereed)
    Abstract [en]

    This paper contains two contributions: 1) A development methodology involving two techniques to enhance the resource utilization and 2) a new generic multi-core resource model for hierarchical scheduling systems.

    As the first contribution, we propose a two-stage development methodology relying on the adjustment of timing attributes in the detailed models during the design stage. We use a lightweight method (statistical model checking) for design exploration, easily assuring high confidence in the correctness of the models. Once a satisfactory design has been found, it can be proved schedulable using the computation costly method (symbolic model checking). In order to analyze a hierarchical scheduling system compositionally, we introduce the notion of a stochastic supplier modeling the supply of resources from each component to its child components in the hierarchy. We specifically investigate two different techniques to widen the set of provably schedulable systems: 1) a new supplier model; 2) restricting the potential task offsets.

    We also provide a way to estimate the minimum resource supply (budget) that a component is required to provide. In contrast to analytical methods, we prove non-schedulable cases via concrete counterexamples. By having richer and more detailed scheduling models this framework, has the potential to prove the schedulability of more systems.

    As the second contribution, we introduce a generic resource model for multi-core hierarchical scheduling systems, and show how it can be instantiated for classical resource models: Periodic Resource Models (PRM) and Explicit Deadline Periodic (EDP) resource models. The generic multi-core resource model is presented in the context of a compositional model-based approach for schedulability analysis of hierarchical scheduling systems.

    The multi-core framework presented in this paper is an extension of the single-core framework used for the analysis in the rest of the paper.

  • 14.
    Braun, Robert
    et al.
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, Faculty of Science & Engineering.
    Nordin, Peter
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, Faculty of Science & Engineering.
    Ericson, Liselott
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, Faculty of Science & Engineering.
    Larsson, L. Viktor
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, Faculty of Science & Engineering.
    Krus, Petter
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems. Linköping University, Faculty of Science & Engineering.
    Pettersson, Maria
    Epiroc Rock Drills AB.
    Hopsan: An Open-Source Tool for Rapid Modelling and Simulation of Fluid and Mechatronic Systems2020In: Proceedings of the BATH/ASME 2020 Symposium on Fluid Power and Motion Control, 2020Conference paper (Refereed)
    Abstract [en]

    Hopsan is an open-source simulation package developed as a collaboration project between industry and academia. The simulation methodology is based on transmission line modelling, which provides several benefits such as linear model scalability, numerical robustness and parallel simulation. All sub-models are pre-compiled, so that no compilation is required prior to starting a simulation. Default component libraries are available for hydraulic, mechanic, pneumatic, electric and signal domains. Custom components can be written in C++ or generated from Modelica and Mathematica. Support for simulation-based optimization is provided using population-based, evolutionary or direct-search algorithms. Recent research has largely focused on co-simulation with other simulation tools. This is achieved either by using the Functional Mock-up Interface standard, or by tool-to-tool communications. This paper provides a description of the program and its features, the current status of the project, and an overview of recent and ongoing use cases from industry and academia.

  • 15.
    Brischetto, Mathias
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Improved Functionality for Driveability During Gear-Shift: A Predictive Model for Boost Pressure Drop2015Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Automated gear-shifts are critical procedures for the driveline as they are demanded to work as fast and accurate as possible. The torque control of a driveline is especially important for the driver’s feeling of driveability. In the case of gear-shifts and torque control in general, the boost pressure is key to achieve good response and thereby a fast gear-shift.

    An experimental study is carried out to investigate the phenomena of boost pressure drop during gear-shift and gather data for the modelling work. Results confirm the stated fact on the influence of boost pressure drop on gear-shift completion time and also indicate a clear linear dependence between initial boost pressure and the following pressure drop.

    A dynamic predictive model of the engine is developed with focus on implementation in a heavy duty truck, considering limitations computational complexity and calibration need between truck configurations. The resulting approach is based on a mean value modelling scheme that uses engine control system parameters and functions when possible. To be able to be predictive, a model for demanded torque and engine speed during the gear-shift is developed as reference inputs to the simulation. The simulation is based on a filling and emptying process throughout the engine dynamics, and yields final values of several engine variables such as boost pressure.

    The model is validated and later evaluated in comparison to measurements gathered in test vehicle experiments and in terms of robustness to input and model deviations. Computer simulations yield estimations of the boost pressure drop within acceptable limits. Consid- ering estimations used prior to this thesis the performance is good. Input deviations and modelling inaccuracies are found to inflict significant but not devastating deviations to the model output, possibly more over time with ageing of hardware taken into account.

    Final implementation in a heavy duty truck ecu is carried out with results indicating that the current implementation of the module is relatively computationally heavy. At the time of ending the thesis it is not possible to analyse its performance further, and it is suggested that the module is optimized in terms of computational efficiency. 

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  • 16.
    Börjesson, Mandus
    et al.
    Linköping University, Department of Science and Technology, Physics, Electronics and Mathematics. Linköping University, Faculty of Science & Engineering.
    Gerner, Håkan
    Linköping University, Department of Science and Technology, Physics, Electronics and Mathematics. Linköping University, Faculty of Science & Engineering.
    Design and implementation of a high-speed PCI-Express bridge2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master thesis will cover the prestudy, hardware selection, design and implementation of a PCI Express bridge in the M.2 form factor. The thesis subject was proposed by WISI Norden who wished to extend the functionality of their hardware using an M.2 module. The bridge fits an M-Key M.2 slot and has the dimensions 80x22 mm. It is able to communicate at speeds up to 8 Gb/s over PCI Express and 200 Mbit/s on any of the 20 LVDS/CMOS pins. The prestudy determined that an FPGA should be used and a Xilinx Artix-7 device was chosen. A PCB was designed that hosts the FPGA as well as any power, debugging and other required systems. Associated proof-of-concept software was designed to verify that the bridge operated as expected. The software proves that the bridge works but requires improvement before the bridge can be used to translate sophisticated protocols. The bridge works, with minor hardware modifications, as expected. It fulfills all design requirements set in the master thesis and the FPGA firmware uses a well-established protocol, making further development easier.

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    Design and implementation of a high-speed PCI-Express bridge
  • 17.
    Cervesato, Iliano
    et al.
    Department of Computer Science, Stanford University, Stanford CA, USA.
    Franceschet, Massimo
    Dipartimento di Matematica e Informatica, Universit, a di Udine, Via delle Scienze, Udine Italy.
    Montanari, Angelo
    Dipartimento di Matematica e Informatica, Universit, a di Udine, Via delle Scienze, Udine Italy.
    The Complexity of Model Checking in Modal Event Calculi with Quantifiers1998Report (Other academic)
    Abstract [en]

    Kowalski and Sergot's Event Calculus (EC) is a simple temporal formalism that, given a set of event occurrences, derives the maximal validity intervals (MVIs) over which properties initiated or terminated by these events hold. It does so in polynomial time with respect to the number of events. Extensions of its query language with Boolean connectives and operators from modal logical have been shown to improve substantially its scarce expressiveness, although at the cost of an increase computational complexity. However, significant sublanguages are still tractable. In this paper, we further extend EC queries by admitting arbitrary event quantification. We demonstrate the added expressive power by encoding a hardware diagnosis problem in the resulting calculus. We conduct a detailed complexity analysis of this formalism and several sublanguages that restrict the way modalities, connectives, and quantifiers can be interleaved. We also describe an implementation in the higher-order logic programming language  lambda  Prolog.

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    fulltext
  • 18.
    Chan, Chun-Jung
    Linköping University, Department of Electrical Engineering.
    Investigation of NoGap: SIMD Datapath Implementation2011Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    Nowadays, many ASIP systems with high computational capabilities are designed in order to fulfill the increasing demands of technical applications. However, the design of ASIP system usually takes many man hours. Therefore, a number of EDA tools are developed to ease the design effort, but they limit the design freedom due to their predefined design templates. Consequently, designers are forced to use lower level HDLs which offer high design flexibility but require substantial design hours. A novel design automation tool called NoGap was proposed to balance such issues. The NoGap system, which is especially used in ASIPs and accelerator design, effectively provides high design flexibility and saves design effort for designers.

    The efficiency and design ability of NoGap were investigated in this thesis work. NoGap was used to implement an eight-way SIMD datapath of an ASIP called Sleipnir, which was devised by the Division of Computer Engineering at Linköping University. For contrast, the manually crafted HDL implementation of the Sleipnir was taken. The critical path implementations, done by both design approaches, were synthesized to the Altera Strtix IV FPGA. The synthesize results showed that the NoGap design although used 1.358 times as many hardware units as the original HDL design. Their timing performance is comparable (HDL/NoGap-60.042/58.156Mhz).

    In this thesis, based on the design experience of SIMD datapath, valuable aspects were suggested to benefit the future users who will use NoGap to implement SIMD structures. In addition, the hidden bugs and insufficient features of NoGap were discovered, and the referable suggestions were provided in order to help the developers to improve the NoGap system.

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    Investigation of NoGap: SIMD Datapath Implementation
  • 19.
    Cherdantseva, Yulia
    et al.
    Cardiff Univ, Wales.
    Burnap, Pete
    Cardiff Univ, Wales.
    Nadjm-Tehrani, Simin
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Jones, Kevin
    Airbus Grp, Wales.
    A Configurable Dependency Model of a SCADA System for Goal-Oriented Risk Assessment2022In: Applied Sciences, E-ISSN 2076-3417, Vol. 12, no 10, article id 4880Article in journal (Refereed)
    Abstract [en]

    A key purpose of a Supervisory Control and Data Acquisition (SCADA) system is to enable either an on-site or remote supervisory control and monitoring of physical processes of various natures. In order for a SCADA system to operate safely and securely, a wide range of experts with diverse backgrounds must work in close rapport. It is critical to have an overall view of an entire system at a high level of abstraction which is accessible to all experts involved, and which assists with gauging and assessing risks to the system. Furthermore, a SCADA system is composed of a large number of interconnected technical and non-technical sub-elements, and it is crucial to capture the dependencies between these sub-elements for a comprehensive and rigorous risk assessment. In this paper, we present a generic configurable dependency model of a SCADA system which captures complex dependencies within a system and facilitates goal-oriented risk assessment. The model was developed by collecting and analysing the understanding of the dependencies within a SCADA system from 36 domain experts. We describe a methodology followed for developing the dependency model, present an illustrative example where the generic dependency model is configured for a SCADA system controlling water distribution, and outline an exemplary risk assessment process based on it.

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  • 20.
    Cuello, Rosandra
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Providing Support for the Movidius Myriad1 Platform in the SkePU Skeleton Programming Framework2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The Movidius Myriad1 Platform is a multicore embedded platform primed to offer high performance and power efficiency for computer vision applications in mobile devices. The challenges of programming multicore environments are well known and skeleton programming offers a high-level programming alternative for parallel computing, intended to hide the complexities of the system from the programmer. The SkePU Skeleton Programming Framework includes backend implementations for CPU and GPU systems and it has the capacity to support more platforms by extending its backend implementations. With this master thesis project we aim to extend the SkePU Skeleton Programming Framework to provide support for execution in the Movidius Myriad1 embedded platform. Our SkePU backend for Myriad1 consists on a set of macros and functions to compose the different elements of a Myriad1 application, data communication structures to exchange data between the host systems and Myriad1, and a helper script and auxiliary files to generate a Myriad1 application.Evaluation and testing demonstrate that our backend is usable, however further optimizations are needed to obtain good performance that would make it practical to use in real life applications, particularly when it comes to data communication. As part of this project, we have outlined some improvements that could be applied to obtain better performance overall in the future, addressing the issues found with the methods of data communication.

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  • 21.
    Da Fontoura, A. A.
    et al.
    Federal University of Rio Grande do Sul, Brazil .
    Nascimento, F.A. M.
    Federal University of Rio Grande do Sul, Brazil .
    Nadjm-Tehrani, Simin
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    De Freitas, E. P.
    Federal University of Rio Grande do Sul, Brazil .
    Timing Assurance of Avionic Reconfiguration Schemes using Formal Analysis2020In: IEEE Transactions on Aerospace and Electronic Systems, ISSN 0018-9251, E-ISSN 1557-9603, IEEE Transactions on Aerospace and Electronic Systems, E-ISSN 1557-9603, Vol. 56, no 1, p. 95-106Article in journal (Refereed)
    Abstract [en]

    Reconfigurable avionics systems can tolerate faults by moving functionalities from failed components to another available system component. This paper proposes a distributed reconfigurable architecture for application migration from failed modules to working ones. The feasible system reconfiguration states are determined off-line to provide the expected configuration in foreseen situations. Model Checking is used to determine feasible configurations evaluating specific temporal properties. A case study is used to show the application of the presented approach as a proof of concept

  • 22.
    Danielsson, Per-Erik
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Implementations of the Convolution Operation1982Report (Other academic)
    Abstract [en]

    The first part of this article surveys a large number of implementations of the convolution operation (which is also known as the sum-of-products, the inner product) based on a systematic exploration of index permutations. First we assume a limited amount of parallelism in the form of an adder. Next, multipliers and RAM:s are utilized. The so called distributed arithmetic follows naturally from this approach.

    The second part brings in the concept of pipelining on the bitlevel to obtain high throughput convolvers adapted for VLSI-design (systolic arrays). The serial/parallel multiplier is analyzed in a way that unravels a vast amount new variations. Even more interesting, all these new variations can be carried over to serial/parallel convolvers. These novel devices can be implemented as linear structures of identical cells where the multipliers are embedded at equidistant intervals.

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    Implementations of the Convolution Operation
  • 23.
    Di Orio, Giovanni
    et al.
    Dept. of Electrotechnical Engineering CTS – UNINOVA, Portugal.
    Rocha, Andre
    Dept. of Electrotechnical Engineering CTS – UNINOVA, Portugal.
    Ribeiro, Luis
    Linköping University, Department of Management and Engineering, Manufacturing Engineering. Linköping University, Faculty of Science & Engineering.
    Barata, Jose
    Dept. of Electrotechnical Engineering CTS – UNINOVA, Portugal.
    The PRIME Semantic Language: Plug and Produce in Standard- based Manufacturing Production Systems2015In: Proceedings of the Flexible Automation and Intelligent Manufacturing Conference, 2015Conference paper (Other academic)
    Abstract [en]

    Nowadays manufacturing production systems are becoming more and more responsive in order to succeed in ahighly unstable environment. The capability of a production system to effectively and efficiently adapt and evolveto face the changing requirements – imposed by volatile and dynamic global markets – is a necessary conditionto enable manufacturing enterprises to be agile. Since the agility of a manufacturing enterprise is always limitedby the agility of its own building blocks than it needs to be spread over the whole enterprise including the operationand information technologies (OT/IT). Turning to production systems, one of the significant challenges isrepresented by the possibility to provide easy and rapid (re-)configuration of their internal components and/orprocesses. Innovative technologies and paradigms have been explored during the years that combined with theincreasing advancement in manufacturing technologies enable the implementation of the “plug and produce”paradigm. The “plug and produce” paradigm is the foundation of any agile production system, since to be agile itis inevitably required to reduce the installation and (re-)engineering activities time – changing/adapting the systemto new requirements – while promoting configuration rather than programming. Therefore, the “plug andproduce” paradigm is a necessary but not sufficient condition for implementing agile production systems. Modernproduction systems are typically known for their plethora of heterogeneous component/equipment. In this complexscenario, the implementation of the “plug and produce” paradigm implies the existence of a well-definedontological model to support components/equipment abstraction with the objective to allow interactions,collaboration and knowledge sharing between them. The PRIME semantic language specifies the semanticstructure for the knowledge models and overall system communication language.

  • 24.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Area Efficient Floating-Point Adder and Multiplier with IEEE-754 Compatible Semantics2014Conference paper (Refereed)
    Abstract [en]

    In this paper we describe an open source floating-point adder andmultiplier implemented using a 36-bit custom number format based onradix-16 and optimized for the 7-series FPGAs from Xilinx. Althoughthis number format is not identical to the single-precision IEEE-754format, the floating-point operators are designed in such a way thatthe numerical results for a given operation will be identical to theresult from an IEEE-754 compliant operator with support forround-to-nearest even, NaNs and Infs, and subnormalnumbers. The drawback of this number format is that the rounding stepis more involved than in a regular, radix-2 based operator. On theother hand, the use of a high radix means that the area costassociated with normalization and denormalization can be reduced,leading to a net area advantage for the custom number format, underthe assumption that support for subnormal numbers is required.

    The area of the floating-point adder in a Kintex-7 FPGA is 261 sliceLUTs and the area of the floating-point multiplier is 235 slice LUTsand 2 DSP48E blocks. The adder can operate at 319 MHz and themultiplier can operate at a frequency of 305 MHz.

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    hrfp_16_icfpt2014.pdf
  • 25.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    EBRAM - Extending the BlockRAMs in FPGAs to support caches and hash tables inan efficient manner2012Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss how a typical Block RAM in an FPGA can be extended to enable the implementation of more efficient caches in FPGAs with very minor modifications to the existing Block RAM architectures. In addition, the modifications also allow other components, such as hash tables, to be implemented more efficiently.

  • 26.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Optimizing Xilinx designs through primitive instantiation2010In: FPGAworld '10 Proceedings of the 7th FPGAworld Conference, New York: ACM , 2010, p. 20-27Conference paper (Refereed)
    Abstract [en]

    This paper is intended as a guideline for people who are interested in manual instantiation of FPGA primitives as a way of improving the performance of an FPGA design. The focus of the paper is on designs where slice primitives like flip-fops and lookup tables are instantiated. Guidelines on how to develop a design with manual instantiation are presented together with a case study of a high performance bitserial two's complement divider where a majority of the area is manually instantiated. This divider is capable of reaching a maximum frequency of 345 MHz in the fastest Virtex-4 while utilizing less than 150 LUTs thanks to the high amount of manual optimizations. An open source library containing modules intended to promote the structured development of modules with manually instantiated components is also presented.

  • 27.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Siverskog, Jacob
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Using Partial Reconfigurability to aid Debugging of FPGA Designs2011Conference paper (Refereed)
    Abstract [en]

    This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.

  • 28.
    Ekudd, Anton
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    Elmätare i mjukvara2020Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
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  • 29.
    Engström, Adam
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Strömsparande arkitektur för inbyggnadslinux2014Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    The objective of this work was to evaluate and implement a number of energy saving functions for a specific embedded system. The functions were then grouped into a number of energy levels with known properties in terms of functionality, energy consumption, and transition time between the levels.

    The embedded system consisted of an AT91 ARM9 processor, GSM/GPRS modem, display, Ethernet and other peripheral units. Some energy saving methods that were considered were suspend to RAM, suspend to disk, frequency scaling, and methods for saving energy in the modem, Ethernet, USB and display backlight. The functions were grouped into levels and an interface was specified for controlling the energy level.

    It proved possible to get known properties within the defined energy levels, even though the paritioning of functions into these levels proved to be sub-optimal in a typical application usage scenario because it was designed for mainly energy consumption, not usage.

    The final result is a number of energy saving functions grouped into levels, which are controllable via an application interface. Each of the levels have a known energy consumption in both loaded and un-loaded mode.

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  • 30.
    Eriksson, Lars
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Nezhadali, Vaheed
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Andersson, Conny
    Linköping University.
    Compressor Flow Extrapolation and Library Design for the Modelica Vehicle Propulsion Library - VehProLib2016In: SAE 2016 World Congress and Exhibition, SAE International , 2016, article id 2016-01-1037Conference paper (Refereed)
    Abstract [en]

    Modelbased systems engineering is becoming an important tool when meeting the challenges of developing the complex future vehicles that fulfill the customers and legislators ever increasing demands for reduced pollutants and fuel consumption. To be able to work systematically and efficiently it is desirable to have a library of components that can be adjusted and adapted to each new situation. Turbocharged engines are complex and the compressor model serves as an in-depth example of how a library can be designed, incorporating the basic physics and allowing fine tuning as more information becomes available. A major part of the paper is the summary and compilation of a set of rules of thumb for compressor map extrapolation. The considerations discussed are extrapolation to surge, extrapolation to restriction region, and extrapolation out to choking. Furthermore the compressor diameter is coupled to the maximum performance of the compressor such as maximum speed, mass flow, and pressure ratio. All this is a result of an analysis of a database of more than 300 compressors. The paper uses the compressor modeling to discuss how wishes for extendability and reuse of component performance influences the library design. A Modelica library named Vehicle Propulsion Library VehProLib has been developed to meet these goals by including basic components that give a starting point for modeling and at the same time allows reuse and extendablility.

  • 31.
    Ernstsson, August
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Griebler, Dalvan
    Pontif Catholic Univ Rio Grande do Sul PUCRS, Brazil.
    Kessler, Christoph
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Assessing Application Efficiency and Performance Portability in Single-Source Programming for Heterogeneous Parallel Systems2023In: International journal of parallel programming, ISSN 0885-7458, E-ISSN 1573-7640, Vol. 51, p. 61-82Article in journal (Refereed)
    Abstract [en]

    We analyze the performance portability of the skeleton-based, single-source multi-backend high-level programming framework SkePU across multiple different CPU-GPU heterogeneous systems. Thereby, we provide a systematic application efficiency characterization of SkePU-generated code in comparison to equivalent hand-written code in more low-level parallel programming models such as OpenMP and CUDA. For this purpose, we contribute ports of the STREAM benchmark suite and of a part of the NAS Parallel Benchmark suite to SkePU. We show that for STREAM and the EP benchmark, SkePU regularly scores efficiency values above 80% and in particular for CPU systems, SkePU can outperform hand-written code.

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  • 32.
    Ernstsson, August
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Vandenbergen, Nicolas
    Julich Supercomp Ctr, Germany.
    Keller, Jörg
    Fernuniv, Germany.
    Kessler, Christoph
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    A Deterministic Portable Parallel Pseudo-Random Number Generator for Pattern-Based Programming of Heterogeneous Parallel Systems2022In: International journal of parallel programming, ISSN 0885-7458, E-ISSN 1573-7640, Vol. 50, p. 319-340Article in journal (Refereed)
    Abstract [en]

    SkePU is a pattern-based high-level programming model for transparent program execution on heterogeneous parallel computing systems. A key feature of SkePU is that, in general, the selection of the execution platform for a skeleton-based function call need not be determined statically. On single-node systems, SkePU can select among CPU, multithreaded CPU, single or multi-GPU execution. Many scientific applications use pseudo-random number generators (PRNGs) as part of the computation. In the interest of correctness and debugging, deterministic parallel execution is a desirable property, which however requires a deterministically parallelized pseudo-random number generator. We present the API and implementation of a deterministic, portable parallel PRNG extension to SkePU that is scalable by design and exhibits the same behavior regardless where and with how many resources it is executed. We evaluate it with four probabilistic applications and show that the PRNG enables scalability on both multi-core CPU and GPU resources, and hence supports the universal portability of SkePU code even in the presence of PRNG calls, while source code complexity is reduced.

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  • 33.
    Faltpihl, Peter
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Ultrasonic sensing design and implementation for detecting and interacting with human beings in an AI system2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis covers the work performed to implement a Sonar sensor solution to detect human beings on a robotic lamp. A previously available solution was evaluated, but had to be redesigned due to faulty electronics. New hardware was developed, together with software to control this hardware. A software implementation of this new Sonar sensor system was also developed, on the robotic lamp itself.

    The nature of this thesis was very practical, so this report will focus on describing the different design stages that were performed, together with a wide discussion about future improvements and work, in order to achieve a robotic lamp that interacts with a human in an interesting manner.

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  • 34.
    Finne, Alice
    et al.
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems.
    Ström, Louise
    Linköping University, Department of Management and Engineering, Fluid and Mechatronic Systems.
    Road Feedback in a Steer-by-Wire System for a Passenger Car: enhancing the feeling of being connected2022Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Road feedback is an essential part of the driving experience, representing a connection betweenthe driver and the vehicle motion. Road feedback in a steer-by-wire system must berecreated and transferred to the driver through a feedback motor mounted on the steeringwheel. This project aimed to implement a function in the feedback motor control with thepurpose of giving the driver road feedback. The function should enhance the drivers trustand confidence in the steering system. Specifically, the function should provide the driverwith a feeling of being connected to the vehicle.

    A pre-study on the subject of steering feel was made as well as an interview study, whichresulted in a list of hypotheses. The hypotheses became a basis for generating conceptideas, together with measurement data of vehicle network signals for different drivingscenarios. Two different functions were then modelled and implemented in MathWorksSimulink. Function 1 models force components acting on the front road wheels in longitudinal,lateral and vertical direction. The forces result in a torque contribution fromeach dimension that acts around the steering axis and represents a reaction in the steeringsystem due to road disturbances. The torque is then translated to a steering wheel torque.Function 2 strives to capture road surface roughness through the high frequency informationin the steering rack motor torque. Three different road surfaces were studied; smoothasphalt, rough asphalt and gravel road.

    A test rig was used in order to verify the behaviour of the functions. The final step of theproject was to implement the functions in a test vehicle, where they could be further tunedand evaluated. The force component models of Function 1 captured different types of roadfeedback which were evaluated separately by timing, authenticity and desirability. Theresult of this evaluation was positive considering them separately. When the models werecombined it resulted in an unwanted behaviour. Function 2 gave torque feedback that feltauthentic and natural, especially for the gravel road case. However, it was more difficult todistinguish different asphalt types. The conclusion was that neither Function 1 nor 2 couldbe approved as finished functions, however both are considered as interesting concepts forfurther development.

    Fully steer-by-wire steering transmissions have now been approved for usage. This meansthat one of the remaining challenges for implementing steer-by-wire cars on today’s marketis the subjective views from the customers. Function 1 and 2 could be a way to providethe drivers with trust towards the steering, and at the same time, enhance the drivingexperience.

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  • 35.
    Fize, Florian
    Linköping University, Department of Computer and Information Science.
    From Theory to Implementation of Embedded Control Applications: A Case Study2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Control applications are used in almost all scientific domains and are subject to timing constraints. Moreover, different applications can run on the same platform which leads to even more complex timing behaviors. However, some of the timing issues are not always considered in the implementation of such applications, and this can make the system fail.

    In this thesis, the timing issues are considered, i.e., the problem of non-constant delay in the control of an inverted pendulum with a real-time kernel running on an ATmega328p micro-controller.

    The study shows that control performance is affected by this problem.

    In addition, the thesis, reports the adaptation of an existing real-time kernel based on an EDF (Earliest Deadline First) scheduling policy, to the architecture of the ATmega328p.

    Moreover, the new approach of a server-based kernel is implemented in this thesis, still on the same Atmel micro-controller.

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  • 36.
    Frate, Marcelo
    et al.
    IFSP, Brazil.
    Rodrigues, Robson Joao Gregorio
    IFSP, Brazil.
    Souza, Gilberto De Tadeu Santos
    Thales Alenia Space, France.
    Lourenco, Euclides
    Linköping University, Department of Computer and Information Science, Human-Centered systems. Linköping University, Faculty of Medicine and Health Sciences.
    Roger, Leonardo Lorenzo Bravo
    Univ Estadual Campinas, Brazil.
    SpuR - A system for spectral signature recognition of chipless RFID tags using Software-Defined Radio2023In: IEEE Latin America Transactions, E-ISSN 1548-0992, Vol. 21, no 10, p. 1114-1121Article in journal (Refereed)
    Abstract [en]

    To solve problems related to Radio Frequency Identification, as well as to develop new technologies and applications with chipless RFID tags, this article describes the development of an innovative reader system based on Software-Defined Radios. Called SpuR, the system proposes a method of reading the spectral signature of RFID tags chipless, using general purpose hardware, reconfigurable by software, and operating in a wide frequency range without the need to change the reading equipment. This approach allows the accurate reading and identification of different types of chipless tags, using a classification procedure, by Euclidean distance, comparing them with a previously stored database.

  • 37.
    Fries, Jakob
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    Johansson, Simon
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Modular 3D Graphics Accelerator for FPGA2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A modular and area-efficient 3D graphics accelerator for tile based rendering in FPGA systems has been designed and implemented. The accelerator supports a subset of OpenGL, with features such as mipmapping, multitexturing and blending. The accelerator consists of a software component for projection and clipping of triangles, as well as a hardware component for rasterization, coloring and video output. Trade-offs made between area, performance and functionality have been described and justified. In order to evaluate the functionality and performance of the accelerator, it has been tested with two different applications.

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  • 38.
    Frisk, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Krysander, Mattias
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Jung, Daniel
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    A Toolbox for Analysis and Design of Model Based Diagnosis Systems for Large Scale Models2017In: IFAC PAPERSONLINE, ELSEVIER SCIENCE BV , 2017, Vol. 50, no 1, p. 3287-3293Conference paper (Refereed)
    Abstract [en]

    To facilitate the use of advanced fault diagnosis analysis and design techniques to industrial sized systems, there is a need for computer support. This paper describes a Matlab toolbox and evaluates the software on a challenging industrial problem, air-path diagnosis in an automotive engine. The toolbox includes tools for analysis and design of model based diagnosis systems for large-scale differential algebraic models. The software package supports a complete tool-chain from modeling a system to generating C-code for residual generators. Major design steps supported by the tool are modeling, fault diagnosability analysis, sensor selection, residual generator analysis, test selection, and code generation. Structural methods based on efficient graph theoretical algorithms are used in several steps. In the automotive diagnosis example, a diagnosis system is generated and evaluated using measurement data, both in fault-free operation and with faults injected in the control-loop. The results clearly show the benefit of the toolbox in a model-based design of a diagnosis system. Latest version of the toolbox can be downloaded at faultdiagnosistoolbox.github.io. (C) 2017, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

  • 39.
    Fritzson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Model-based development of sustainable cyber-physical systems including requirement formalization using the OpenModelica Model-based Development Toolkit2016In: ACM PROCCEDINGS OF THE 10TH EUROPEAN CONFERENCE ON SOFTWARE ARCHITECTURE WORKSHOPS (ECSA-W), ASSOC COMPUTING MACHINERY , 2016Conference paper (Refereed)
    Abstract [en]

    Large-scale and increasingly software-defined systems in power and factory automation are very long-lived. Longevity requires sustainability-economically, environmentally and last but not least in terms of usability. Sustainability therefore requires continuous change. In this talk we look at handling requirements, models, and implementations in a model-driven formal way that lends itself to a more systematic change tracking than traditional software development approaches and languages, but that also crosses boundaries of software-controlled physical equipment models (so-called cyber-physical systems), distributed digital control (networked systems) and software services. The industry is currently seeing a rapid development of cyber-physical system products. The systems that are developed have increasing demands of sustainability, dependability and usability. Moreover, lead time and cost efficiency continue to be essential for industry competitiveness. Extensive use of modeling and simulation - Model-Based Systems Engineering (MBSE) tools - throughout the value chain and system life-cycle is one of the most important ways to effectively target these challenges. Simultaneously there is an increased interest in open source tools that allow more control of tool features and support, and increased cooperation and shared access to knowledge and innovations between organizations. In this talk we briefly present technology and open source tooling for MBSE based on the Modelica and UML standards, supported by tools such as OpenModelica and Papyrus respectively. Modelica is a modern, strongly typed, declarative, equation-based, and object-oriented language for modeling and simulation of complex cyber-physical systems, whereas UML is a wide-spread industrial standard for software modeling. We present the OpenModelica open source MBSE environment including the ModelicaML Eclipse plug-in integrating Modelica and UML, covering the development process starting from business processes, via requirements, to models, which can be compiled to simulations or to product code. An important question is whether a particular system design fulfills or violates requirements that are imposed on the system under development. We give examples of case studies starting with natural-language requirements and show briefly how they are translated into models. Then, designs and verification scenarios are modeled, and simulation models are composed and simulated automatically. The simulation results produced can then be used to draw conclusions on requirement fulfillment. Other features of the environment are meta modeling for efficient model transformations, the Functional Mockup Interface for general tool integration, model-based optimization, as well as generation of parallel code for multi-core architectures.

  • 40.
    Garro, Alfredo
    et al.
    Department of Informatics, Modeling, Electronics and Systems Engineering (DIMES), University of Calabria, Italy.
    Tundis, Andrea
    Department of Informatics, Modeling, Electronics and Systems Engineering (DIMES), University of Calabria, Italy.
    Bouskela, Daniel
    R&D Division, Electricité de France (EDF), France.
    Jardin, Audrey
    R&D Division, Electricité de France (EDF), France.
    Nguyen, Thuy
    R&D Division, Electricité de France (EDF), France.
    Otter, Martin
    Institute of System Dynamics and Control, DLR German Aerospace Center, Germany.
    Buffoni, Lena
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Fritzson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Sjölund, Martin
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Schamai, Wladimir
    Airbus Group Innovations, Hamburg, Germany.
    Olsson, Hans
    Dassault Systèmes AB, Sweden.
    On formal cyber physical system properties modeling: a new temporal logic language and a Modelica-based solution2016In: 2016 IEEE International Symposium on Systems Engineering (ISSE), IEEE , 2016, p. 112-119Conference paper (Refereed)
    Abstract [en]

    Modeling and Simulation methods, tools and techniques aim at supporting the different phases of the lifecycle of modern systems, going from requirements analysis to system design and operation. However, their effective application requires investigating several aspects such as the formal modeling of system requirements and the binding and automated composition between heterogeneous models (e.g. requirements models, architectural models, behavioral models). In this context, the paper presents a new formal requirement modeling language based on temporal logic, called FORM-L, and a software library, based on the Modelica language, that implements the constructs provided by FORM-L so as to enable the visual modeling of system properties as well as their verification through simulation. The effectiveness of the proposal is shown on a real case study concerning an Intermediate Cooling System.

  • 41.
    Gorm Larsen, Peter
    et al.
    Aarhus University, Denmark.
    Fitzgerald, John
    Newcastle University, England.
    Woodcock, Jim
    University of York, England.
    Fritzson, Peter
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Brauer, Joerg
    Verified Syst Int, Germany.
    Kleijn, Christian
    Controllab Prod, Netherlands.
    Lecomte, Thierry
    Clearsy SAS, France.
    Pfeil, Markus
    TWT Science and Innovat, Germany.
    Green, Ole
    Agro Intelligence, Denmark.
    Basagiannis, Stylianos
    United Technology Research Centre, Ireland.
    Sadovykh, Andrey
    Softeam, France.
    Integrated Tool Chain for Model-based Design of Cyber-Physical Systems: The INTO-CPS Project2016In: 2016 2ND INTERNATIONAL WORKSHOP ON MODELLING, ANALYSIS, AND CONTROL OF COMPLEX CPS (CPS DATA), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    We describe INTO-CPS, a project that aims to realise the goal of integrated tool chains for the collaborative and multidisciplinary engineering of dependable Cyber-Physical Systems (CPSs). Challenges facing model-based CPS engineering are described, focussing on the semantic diversity of models, management of the large space of models and artefacts produced in CPS engineering, and the need to evaluate effectiveness in industrial settings. We outline the approach taken to each of these issues, particularly on the use of semantically integrated multi-models, links to architectural modelling, code generation and testing, and evaluation via industry-led studies. We describe progress on the development of a prototype tool chain from baseline tools, and discuss ongoing challenges and open research questions in this area.

  • 42.
    Gratorp, Eric
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    Evaluation of online hardware video stabilization on a moving platform2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Recording a video sequence with a camera during movement often produces blurred results. This is mainly due to motion blur which is caused by rapid movement of objects in the scene or the camera during recording. By correcting for changes in the orientation of the camera, caused by e.g. uneven terrain, it is possible to minimize the motion blur and thus, produce a stabilized video.

    In order to do this, data gathered from a gyroscope and the camera itself can be used to measure the orientation of the camera. The raw data needs to be processed, synchronized and filtered to produce a robust estimate of the orientation. This estimate can then be used as input to some automatic control system in order to correct for changes in the orientation

    This thesis focuses on examining the possibility of such a stabilization. The actual stabilization is left for future work. An evaluation of the hardware as well as the implemented methods are done with emphasis on speed, which is crucial in real time computing.

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  • 43.
    Gunhardson, Erica
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Indoor Positioning Using Angle of Departure Information2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    I detta examensarbete undersöks möjligheten att kunna använda en positioneringsmetod som inte enbart förlitar sig på den uppmätta signalstyrkan. Istället används en metod som bestämmer från vilken vinkel en signal uppkommer ifrån. Den här tekniken kallas för direction-finding. När informationen om signalens vinkel fastställts används den i ett positioningsfilter som uppskattar positionen. Två tillvägagångssätt har använts i den här rapporten, ett där enbart vinkeln används och ett där både signalstyrka och vinkel används.

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  • 44.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Hellman, Noah
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Approximate Floating-Point Operations with Integer Units by Processing in the Logarithmic Domain2021In: 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 45-52Conference paper (Refereed)
    Abstract [en]

    Floating-point numbers represented using a hidden one can readily be approximately converted to the logarithmic domain using Mitchell's approximation. Once in the logarithmic domain, several arithmetic operations including multiplication, division, and square-root can be easily computed using the integer arithmetic unit. This has earlier been used in fast reciprocal square-root algorithms, sometimes referred to as magic number algorithms. The proposed approximate operations are realized by performing an integer operation using an integer unit on floating-point data and adding an integer constant to obtain the approximate floating-point result. In this work, we derive easy to use equations and constants for multiple floating-point formats and operations.

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  • 45.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Basic Arithmetic Circuits2017In: Arithmetic Circuits for DSP Applications / [ed] Pramod Kumar Meher, Thanos Stouraitis, John Wiley & Sons, 2017, p. 1-32Chapter in book (Other academic)
    Abstract [en]

    General‐purpose DSP processors, application‐specific processors, and algorithm‐specific processors are used to implement different types of DSP systems or subsystems. They are typically used in applications involving complex and irregular algorithms while application‐specific processors provide lower unit cost and higher performance for a specific application, particularly when the volume of production is high. Most DSP applications use fractional arithmetic instead of integer arithmetic. Multimedia and communication applications involve real‐time audio and video/image processing which very often require sum‐of‐products (SOP) computation. The need of computing non‐linear functions arises in many different applications. The straightforward method of approximating an elementary function is to just store the values in a look‐up table typically leads to large tables, even though the resulting area from standard cell synthesis grows slower than the number of memory bits. It is of interest to find ways to approximate elementary functions using a trade‐off between arithmetic operations and look‐up tables.

  • 46.
    Gustafsson, Robin
    et al.
    Linköping University, Department of Computer and Information Science.
    Blomqvist, Niklas
    Linköping University, Department of Computer and Information Science.
    Options handling using external devices in forklift trucks2016Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Unique customizations (options) of features in forklifts are often requested by customers. When new options are created or existing options have to be modified in the main software the complexity increases, the firmware revision pool gets large and with the increasing code size the memory limit is threatened.

    This affects the software development since the frequent modification of the option handler software is very resource consuming. Therefore it is desirable to have a highly modular system for the option handler to simplify the development process. Although the market value of this improvement is negligible the possible long term savings is the desirable effect.

    This thesis explores the possibility of migrating the option handling software to a dedicated hardware module. This helps the development process by increasing the modularity of the system architecture and thus reducing the development scope. The tools and the approach to accomplish this option handler is analyzed. A system model of the resulting approach is designed and a prototype is developed to validate the result.

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  • 47.
    Hag, Juni
    Linköping University, Department of Science and Technology, Physics, Electronics and Mathematics. Linköping University, Faculty of Science & Engineering.
    Implementation and performance analysis of multiple concurrent WPAN protocols on a system-on-chip2022Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The development of new energy efficient Wireless Personal Area Network (WPAN) protocols is a big factor for the increased interest in Internet of Things (IoT). However, the many protocols with overlapping applications have led to competing standards and sensor networks using different protocols, even to perform the same tasks. If different sensors in IoT uses different protocols in the same area, a single gateway connecting to all of them must support all their protocols simultaneously. This thesis studies latency, average sending time and range for Bluetooth Low Energy (BLE), 802.15.4 and Zigbee in multiprotocol mode on the nRF52840 System on Chip (SoC). In addition, an 802.15.4-based protocol synchronizing with the BLE frames using Time Division Multiple Access (TDMA) techniques was designed and implemented. This protocol could be used in sensor networks using both the BLE and 802.15.4 protocols to assure the 802.15.4-based devices will not try to transmit during the periods the gateway is busy with other communications.

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  • 48.
    Hejdström, Christoffer
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Using HLS for Acceleration of FPGA Development: A 3780-Point FFT Case Study2022Independent thesis Advanced level (degree of Master (Two Years)), 28 HE creditsStudent thesis
    Abstract [en]

    Manually designing hardware for fpga implementations is time consuming. Onepossible way to accelerate the development of hardware is to use high level syn-thesis (hls) tools. Such tools synthesizes a high level model written in a languagesuch as c++ into hardware. This thesis investigates hls and the efficacy of using hls in the hardware design flow.

    A 3780-point fast Fourier transform optimized for area is used to compare Vitis hls with a manual hardware implementation. Different ways of writing the highlevel model used in hls and their impacts in the synthesized hardware together with other optimizations is investigated.

    This thesis concludes that the results from the hls implementation are not comparable with the manual implementation, they are significantly worse. Further, high level code written from a non-hardware point of view needs to be rewritten from a hardware point of view to provide good results. The use of high level synthesis is not best used by designers from an algorithm or software background, but rather another tool for hardware designers. High level synthesis can be used as an initial design tool, allowing for quick exploration of different designs andarchitectures.

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  • 49.
    Hinnerson, Martin
    Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Resource Efficient, HighSpeed FPGA Implementation of Lossless Image Compression for 3D Vision2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless compression algorithms and the implementation operate at 214.3 MHz with a max throughput of 3.43 Gbit/s. The compression ratio is compared to that of competing implementations from Teledyne DALSA Inc. and Pleora Technologies on a set of typical 3D range data images. The proposed algorithm achieve a higher compression ratio while maintaining a small hardware footprint.

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  • 50.
    Holmberg, Gunnar
    Linköping University, Department of Mechanical Engineering. Linköping University, The Institute of Technology.
    On Aircraft Development: managing complex systems with long life cycles2003Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Time plays an important role for the development of aircraft. The aircraft has a long life cycle and is composed of many systems with life cycles that sometimes differ with an order of magnitude in relation to the overall system. Aerospace and defense systems are subject to increasing systems of system integration, a globalized industry and in general more demand for change over its life.

    This thesis is based on clinical research. It combines experience from aerospace industry with general frameworks for product development such as: axiomatic design, the clockspeed framework and C-K theory. The purpose is to identify good development practice for future aerospace and defense systems development. The aircraft is here considered as a system with general properties such as high complexity with a long life and need for flexibility and integrity. Emphasis in the analysis is on time aspects.

    The life cycle is described for individual technologies as well as for the complex system. The development is analyzed in the dimensions of product, process and supply chain followed by a more general analysis. In the product dimension, axiomatic design is used to identify some ideal properties for a flexible system. The process dimension covers experiences and aspects on how to perform integrated product development, including identified success factors from experiences at Saab. In the supply chain dimension aspects of the supply chain for the actual type of systems are covered.

    The complex system is studied in its context. The coupling between the system flexibility and requirement stability is used to analyze properties of the system. It is pointed out that the system should be balanced such that domains of the system that are subject to stable requirements could be optimized and areas where requirements vary should be flexible and prepared for change. From this follows the need to have differentiated processes and supply chain strategies that supports the establishment of these properties in the system.

    The development capability is analyzed with focus on the extended enterprise, and the conditions in horizontal and vertical collaboration. In particular these aspects are studied based on Saab experiences for the possibility to combine the roles of being integrator, and supplier. The combination of different requirements for the two situations is addressed with a combination of core and interface processes in a so- called life buoy approach.

    Innovation is often highly constrained in the complex system context. The ideal system architecture proposed relaxes constraints for innovation. In addition, some properties of innovation in the complex system are discussed and in particular the application of demonstrators is discussed as a possible tool to orientate in an innovation intense environment.

    The thesis conclusions covers general aspects on how to balance between the three dimensions and how to decompose and differentiate such that it is possible to meet requirements with a strong need for optimization combined with requirements where there is a strong need to adapt over the life. Time considerations are found to support this decomposition and differentiation.

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