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  • 1.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic)
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

  • 2.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, 79-90 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

  • 3.
    Andersson, Niklas
    et al.
    Ericsson Microelectronics AB.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Models and Implementation of a Dynamic Element Matching DAC2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, 7-16 p.Article in journal (Refereed)
    Abstract [en]

    The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been suggested as a promising method to improve matching between the DAC''s reference levels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process. The measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable performance.

  • 4.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, 43-53 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

  • 5.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, 87-98 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

  • 6.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Qazi, Fahad
    Catena AB, Stockholm, Sweden .
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Analysis and design of low noise transconductance amplifier for selective receiver front-end2015In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, 361-372 p.Article in journal (Refereed)
    Abstract [en]

    Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

  • 7.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design and analysis of high-speed split-segmented switched-capacitor DACs2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 92, no 2, 199-217 p.Article in journal (Refereed)
    Abstract [en]

    In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (WCu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

    The full text will be freely available from 2018-04-26 17:41
  • 8.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design and Analysis of High Speed Capacitive Pipeline DACs2014In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, 359-374 p.Article in journal (Refereed)
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

  • 9.
    Eklund, Jan-Erik
    et al.
    Infineon Techn. Linköping.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Influence of metastability errors on SNR in successive-approximation A/D converters.2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, 191-198 p.Article in journal (Refereed)
  • 10.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 69-78 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 11.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 241-247 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

  • 12.
    Gao, YC
    et al.
    Royal Inst Technol, Elect Syst Design Lab, S-16440 Kista, Sweden Ericsson Microelect AB, SE-58117 Linkoping, Sweden.
    Wikner, JJ
    Tenhunen, H
    Royal Inst Technol, Elect Syst Design Lab, S-16440 Kista, Sweden Ericsson Microelect AB, SE-58117 Linkoping, Sweden.
    Design and analysis of an oversampling D/A converter in DMT-ADSL systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, 201-210 p.Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.

  • 13.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, 201-210 p.Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 14.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, 201-210 p.Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunicationapplications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigmadeltamodulators are needed to meet the dynamic performance requirements. This paper presents an oversamplingDAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the highorderone-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limitcycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. Fromour analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator havenon-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients isprovided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented ina 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 15.
    Khan, Hashim Raza
    et al.
    Department of Electronic Engineering, Electronics Design Centre, NED University of Engineering & Technology, Karachi, Pakistan.
    Qureshi, Abdul Raheem
    Department of Electronic Engineering, Electronics Design Centre, NED University of Engineering & Technology, Karachi, Pakistan; Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Delft, The Netherlands.
    Zafar, Faiza
    Department of Electronic Engineering, Electronics Design Centre, NED University of Engineering & Technology, Karachi, Pakistan.
    Wahab, Qamar ul
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, Faculty of Science & Engineering.
    Design of a broadband current mode class-D power amplifier with harmonic suppression2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 89, no 1, 15-24 p.Article in journal (Refereed)
    Abstract [en]

    Current mode class-D power amplifiers (CMCD-PA) are attractive for fully integrated PA implementation as the output capacitance of the active device can be absorbed in the output matching network that can be realized with minimum number of components. This paper presents a simplified design approach for CMCD PA design using an integrated balun transformers. Expressions are derived for the optimum device sizing for second harmonic suppression resulting in improved efficiency. An expression of amplifier efficiency as a function of device size is is presented proving that current mode class-D amplifier yields higher higher efficiency than a class-E amplifier for the same device size. The amplifier is implemented in 130 nm CMOS process and encapsulated in QFN package. Measurement results show that the amplifier exhibits broadband response between 1.4 and 2.1 GHz with peak output power of 26.8 dBm at 1.8 GHz using a 2.4 V supply. PAE remains above 40 % for the entire range while peak PAE is 48 %. Results show a good match between simulation and measurement work. Voltage sweep of the amplifier shows that it can be used in supply modulation based LINC techniques.

  • 16.
    Pillai, Anu Kalidas Muralidharan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Efficient signal reconstruction scheme for M-channel time-interleaved ADCs2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 2, 113-122 p.Article in journal (Refereed)
    Abstract [en]

    In time-interleaved analog-to-digital converters (TI-ADCs), the timing mismatches between the channels result in a periodically nonuniformly sampled sequence at the output. Such nonuniformly sampled output limits the achievable resolution of the TI-ADC. In order to correct the errors due to timing mismatches, the output of the TI-ADC is passed through a digital time-varying finite-length impulse response reconstructor. Such reconstructors convert the nonuniformly sampled output sequence to a uniformly spaced output. Since the reconstructor runs at the output rate of the TI-ADC, it is beneficial to reduce the number of coefficient multipliers in the reconstructor. Also, it is advantageous to have as few coefficient updates as possible when the timing errors change. Reconstructors that reduce the number of multipliers to be updated online do so at a cost of increased number of multiplications per corrected output sample. This paper proposes a technique which can be used to reduce the number of reconstructor coefficients that need to be updated online without increasing the number of multiplications per corrected output sample.

  • 17.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Multiband RF-Sampling Receiver Front-End with On-Chip Testability in 0.13μm CMOS2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 2, 115-127 p.Article in journal (Refereed)
    Abstract [en]

    In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 29 subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole frontend have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

  • 18.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    CMOS blocks for on-chip RF test2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, 151-150 p.Article in journal (Refereed)
    Abstract [en]

    In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.

  • 19.
    Raza Khan, Hashim
    et al.
    NED University of Engn and Technology, Pakistan .
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ul Wahab, Qamar
    NED University of Engn and Technology, Pakistan .
    A parallel circuit differential class-E power amplifier using series capacitance2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 75, no 1, 31-40 p.Article in journal (Refereed)
    Abstract [en]

    Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 mu m CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.

  • 20.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 215-222 p.Article in journal (Refereed)
    Abstract [en]

    A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade‐offs. The redundancy removes the need to control comparator offsets, allowing the large process‐variation induced mismatch of small devices in nanometer technologies. This enables the use of small‐sized, ultra‐low‐power comparators with clock‐gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low‐power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

  • 21.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    The blocker challenge when implementing software defined radio receiver RF frontends2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 2, 81-89 p.Article in journal (Refereed)
    Abstract [en]

    Key blocker requirements of software defined radio receivers are identified from first principles. Three challenges are derived from these requirements, the need for passive filter banks or tunable passive filters, a very highly linear RF front-end and a high performance analog-to-digital converter. Each of these challenges is analyzed regarding possible solutions in the context of state-of-the art technology.

  • 22.
    Svensson, Christer
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power consumption of analog circuits: a tutorial2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 65, no 2, 171-184 p.Article in journal (Refereed)
    Abstract [en]

    A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.

  • 23.
    Svärd, Daniel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jansson, Christer
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A readout IC for an uncooled microbolometer infrared FPA with on-chip self-heating compensation in 0.35 mu m CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 29-44 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes a readout integrated circuit architecture for an infrared focal plane array intended for infrared network-attached video cameras in surveillance applications. The focal plane array consists of 352 x 288 uncooled thin-film microbolometer detectors with a pitch of 25 mu m, enabling ambient temperature operation. The circuit features a low-noise readout path, detector resistance mismatch correction and a non-linear ramped current pulse scheme for the electrical biasing of the detectors in order to relax the dynamic range requirement of amplifiers and the ADC in the readout channel, imposed by detector process variation and self-heating during readout. The design is implemented in a 0.35-mu m standard CMOS process and two versions of a smaller 32 x 32-pixel test chip have been fabricated and measured for evaluation. The latest test chip achieves a dynamic range of 97 dB and an input-referred RMS noise voltage of 6.4 mu V yielding an estimated NETD value of 26 mK with f/1 optics. At a frame rate of 60 FPS the chip dissipates 170 mW of power from a 3.4 V supply.

  • 24.
    Wang, Yinan
    et al.
    National University of Def Technology, Peoples R China.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Xu, Hui
    National University of Def Technology, Peoples R China.
    Diao, Jietao
    National University of Def Technology, Peoples R China.
    Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 2, 275-288 p.Article in journal (Refereed)
    Abstract [en]

    In order to enhance the effective resolution of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear channel mismatches should be carefully calibrated. This paper concentrates on a bandwidth-efficient background calibration method for nonlinear errors in M-channel TI-ADCs. It utilizes the least-mean square algorithm as well as a certain degree of oversampling to achieve adaptive mismatch tracking. The calibration performance and computational complexity are investigated and evaluated through behavioral-level simulations. Furthermore, a calibration strategy for narrow-band input signals is proposed and verified as an improvement of the basic calibration structure for such signals.

  • 25.
    Wanhammar, Lars
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Guest editorial2008In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 54, no 2, 75-76 p.Article in journal (Other academic)
  • 26.
    Wikner, Jacob
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Tan, Nianxiong
    Globespan Semiconducter, Inc., Red Bank, NJ, USA.
    Influence of Circuit Imperfections on the Performance of DACs1999In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 18, no 1, 7-20 p.Article in journal (Refereed)
    Abstract [en]

    Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the performance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit components (such as output impedance, mismatch, circuit noise, etc.) on the frequency-domain performance. Both deterministic and stochastic effects are modeled. The purpose of this modeling is to provide an insightful design guide for high dynamic performance CMOS digital-to-analog converters.

1 - 26 of 26
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