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  • 1.
    Eghbali, Amir
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A Multimode Transmultiplexer Structure2008In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 55, no 3, p. 279-283Article in journal (Refereed)
    Abstract [en]

    This paper introduces a multimode transmultiplexer (TMUX) structure capable of generating a large set of user-bandwidths and center frequencies. The structure utilizes fixed integer sampling rate conversion (SRC) blocks, Farrow-based variable interpolation and decimation structures, and variable frequency shifters. A main advantage of this TMUX is that it needs only one filter design beforehand. Specifically, the filters in the fixed integer SRC blocks as well as the subfilters of the Farrow structure are designed only once. Then, all possible combinations of bandwidths and center frequencies are obtained by properly adjusting the variable delay parameter of the Farrow-based filters and the variable parameters of the frequency shifters. The paper includes examples for demonstration. It also shows that, using the rational SRC equivalent of the Farrow-based filters, the TMUX can be described in terms of conventional multirate building blocks which may be useful in further analysis of the overall system.

  • 2.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Lower bounds for constant multiplication problems2007In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 54, no 11, p. 974-978Article in journal (Refereed)
    Abstract [en]

    Lower bounds for problems related to realizing multiplication by constants with shifts, adders, and subtracters are presented. These lower bounds are straightforwardly calculated and have applications in proving the optimality of solutions obtained by heuristics.

  • 3. Gustavsson, M
    et al.
    Tan, NXN
    Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden GlobeSpan Inc, Red Bank, NJ 07701 USA.
    A global passive sampling technique for high-speed switched-capacitor time-interleaved ADCs2000In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 47, no 9, p. 821-831Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a passive sampling technique for time-interleaved switched capacitor analog-to-digital converters (ADCs), The purpose of the proposed sampling technique is to reduce the effect of delay skews between the sample and hold (S/H) circuits in the parallel channels, which limits the performance at high signal frequencies, If designed properly, the circuit can reduce the delay-skew related distortion by 10-20 dB compared to an architecture without a global input S/H circuit. Since no op amp needs to work at the full speed of the ADC, the circuit is suitable for high-speed and consumes less power than an architecture with an active input S/H circuit.

  • 4.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Hermanowicz, Ewa
    A complex variable fractional-delay FIR filter structure2007In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 54, no 9, p. 785-789Article in journal (Refereed)
    Abstract [en]

    This brief introduces a structure for complex variable fractional delay (FD) finite-length impulse response (FIR) filters. The structure is derived from a real variable FD FIR filter and is constituted by a set of fixed real linear-phase FIR filters and two multiply-accumulate chains containing variable multipliers. In this way the implementation complexity and delay may be reduced in comparison with the cascade approach which hitherto has been used for the same purpose. A design example is included to demonstrate the benefits of the new structure. © 2007 IEEE.

  • 5.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering.
    On linear-phase FIR filters with variable bandwidth2004In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 51, no 4, p. 181-184Article in journal (Refereed)
    Abstract [en]

    Recently, a particular structure for linear-phase finite-impulse response (FIR) filters with a variable bandwidth has received attention. In this structure, the overall transfer function is a weighted linear combination of fixed subfilters, with the weights being directly determined by the bandwidth. An advantage of this structure is that there are only a few adjustable parameters (weights), which results in a simple updating routine. However, in this paper, it is demonstrated that the use of a number of fixed regular overdesigned filters, each taking care of a part of the frequency region, in fact results in a lower overall arithmetic complexity. The price to pay is an increased group and phase delay.

  • 6.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    On the design of adjustable fractional delay FIR filters2003In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 50, no 4, p. 164-169Article in journal (Refereed)
    Abstract [en]

    This brief considers minimax design of adjustable fractional delay finite-impulse response (FIR) filters. We employ a filter structure that, in the paper by Vesma and SaramΣki in 1997, is referred to as the modified Farrow structure which makes use of a number of linear-phase FIR subfilters. Previously, only the cases where all subfilters are of equal orders have been considered. In this brief, we propose a design technique that in general produces subfilters of different orders which results in a lower overall arithmetic complexity. Design examples are included, illustrating the efficiency of the proposed design technique.

  • 7.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Filter structures composed of all-pass and FIR filters for interpolation and decimation by a factor of two1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 7, p. 896-905Article in journal (Refereed)
    Abstract [en]

    This paper introduces filter structures for interpolation and decimation by a factor of two. The structures are derived by using the frequency-response masking approach, in which the overall filter makes use of a periodic model filter, its complementary filter, and two masking filters. The periodic model filters are obtained by replacing each delay element in a model filter with M delay elements in cascade. The model filter is a half-band infinite-impulse response (IIR) filter composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. In the final interpolator and decimator structures the filtering takes plate at the lowest of the two sampling rates involved. The corresponding overall filter can be designed by separately optimizing a half-band IIR filter and a linear-phase FIR filter. Both nonlinear-phase and approximately linear-phase filters are considered. One advantage of the proposed filter structures over conventional half-band IIR filter structures is that their maximal sample frequency is M times higher, which may be utilized to increase the speed in an implementation and/or to reduce the power consumption via power supply voltage scaling techniques. In the case of approximately linear-phase filters, the computational complexity can be reduced as well. Several design examples are included demonstrating the properties and advantages of the proposed filter structures

  • 8.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    High-speed recursive digital filters based on the frequency-response masking approach2000In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 47, no 1, p. 48-61Article in journal (Refereed)
    Abstract [en]

    The frequency-response masking approach for high-speed recursive infinite-impulse response (IIR) digital filters is introduced. In this approach, the overall filter consists of a periodic model filter, its power-complementary periodic filter, and two masking filters. The model filters are composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. The transfer functions of the all-pass filters are functions of zM, which implies that the maximal sample frequency for the overall filter is M times that of the corresponding conventional IIR filter. The maximal sample frequency can be increased to an arbitrary level for arbitrary bandwidths. The overall filter can be designed by separately optimizing the model and masking filters with the aid of conventional approximation techniques. The obtained overall filter also serves as a good initial filter for further optimization. Both nonlinear-phase and approximately linear-phase filters are considered. By using the new approach, the potential problems of pole-zero cancellations, which are inherent in algorithm transformation techniques, are avoided. Further, robust filters under finite-arithmetic conditions can always be obtained by using wave-digital all-pass filters and non-recursive FIR filters. Several design examples are included illustrating the properties of the new filters.

  • 9.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    High-speed recursive filter structures composed of identical all-pass subfilters for interpolation, decimation, and QMF banks with perfect magnitude reconstruction1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 1, p. 16-28Article in journal (Refereed)
    Abstract [en]

    High-speed recursive filter structures for interpolation and decimation with factors of two, and quadrature mirror filter (QMF) banks with perfect magnitude reconstruction, are proposed. The structures are composed of identical all-pass subfilters that are interconnected via extra multipliers. For the case of interpolation and decimation filters, the overall transfer function corresponds in the simplest case to several half-band infinite-impulse response (IIR) filters in cascade. To achieve a smaller passband ripple than for a cascade design, a design procedure that has been used earlier for single-rate filters is used. In this approach, the design is split into designs of a prototype finite-impulse response (FIR) filter and a half-band IIR filter. For the case of QMF banks, the design is again separated into designs of a prototype FIR filter and a half-band IIR filter. One major advantage of the proposed filter structures over the corresponding conventional (half-band filter) structures is that the required coefficient word length for the all-pass filters is substantially reduced, implying that the maximal sample frequency can he substantially increased for a given VLSI technology. Further, for interpolation and decimation, the arithmetic complexity may be reduced in comparison with both the conventional structures and straightforward cascade structures. Simple recurrence formulas for computation of the interconnecting multipliers, given the overall transfer function, are derived. Several examples are included which compare the proposed structures with the corresponding conventional and straightforward cascade structures.

  • 10.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wave digital filter structures for high-speed narrow-band and wide-band filtering1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 6, p. 726-741Article in journal (Refereed)
    Abstract [en]

    Wave digital filter (WDF) structures for high-speed narrow-band and wide-band filtering are introduced. The narrow-band filter is composed of a periodic model filter and one or several, possibly periodic, masking filters in cascade. Lattice and bireciprocal lattice WDF filters are used for the model and masking filters, respectively. The wide-band filter consists of a narrow-band filter in parallel with an all-pass filter. The overall filters can be designed by separately designing the model and masking filters. The filters obtained in this approach also serve as good initial filters for further optimization. Both nonlinear and approximately linear phase filters are considered. One major advantage of the new filters over the corresponding conventional filters is that they have a substantially higher maximal sample frequency. In the case of approximately linear phase, the computational complexity can also be reduced. Further, the use of bireciprocal lattice wave digital (WD) masking filters also makes it possible to reduce the complexity, compared with the case in which FIR masking filters are used. Several design examples and a discussion of finite wordlength effects are included for demonstrating the properties of the new filters.

  • 11.
    Lindgren, Leif
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A new simultaneous multislope ADC architecture for array implementations2006In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 53, no 9, p. 921-925Article in journal (Refereed)
    Abstract [en]

    This brief presents a new simultaneous multislope analog-digital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture

  • 12.
    Löwenborg, Per
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    First-order sensitivity of complementary diplexers2004In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 51, no 8, p. 421-425Article in journal (Refereed)
    Abstract [en]

    This paper provides sensitivity analysis of complementary diplexers which are used for dividing the frequency spectrum into two adjacent frequency bands. Analytical expressions of the semirelative first-order sensitivity of the transducer losses are derived. These sensitivity expressions indicate that the passband loss sensitivity of a complementary diplexer is substantially lower than that of doubly resistively terminated reactance networks which are known to have a low sensitivity. Numerical simulations are included, supporting the theoretical results. © 2004 IEEE.

  • 13.
    Löwenborg, Per
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters2003In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 50, no 7, p. 355-367Article in journal (Refereed)
    Abstract [en]

    Multirate filter banks make use of analysis and synthesis filter banks. This paper introduces two-channel digital and hybrid analog/digital multirate filter banks where either the analysis or synthesis filters have a very low complexity. Such filter banks find application, for example, in high-speed analog-to digital converters where it is essential to minimize the complexity of the discrete-time or analog filters. The proposed digital filter banks are approximately perfect reconstruction (PR) filter banks, whereas the hybrid analog/digital filter banks can be chosen to be either approximately PR or approximately perfect magnitude reconstruction filter banks. The design is performed by first optimizing the digital or analog analysis filters and then, with the analysis filters fixed, optimizing the digital synthesis filters. This design procedure makes it possible to obtain analysis filters of very low order and complexity. The overall complexity is also low. Further, the proposed filter banks are, in all cases, very easy to design by making use of well-known and reliable optimization techniques, in particular, as small distortion and aliasing as desired are readily obtained because they are controlled in a linear programming problem. Several design examples are included, illustrating the properties of the proposed filter banks.

  • 14.
    Martinez-Peiro, M.
    et al.
    School of Telecommunication Engineering, Department of Electronic Engineering, Universidad Politecnica de Valencia, 46020 Valencia, Spain.
    Boemo, E.I.
    School of Computer Engineering, Universidad Autonoma de Madrid, 28049 Madrid, Spain.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm2002In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 49, no 3, p. 196-203Article in journal (Refereed)
    Abstract [en]

    In this work, a new algorithm called nonrecursive signed common subexpression elimination (NR-SCSE) is discussed, and several Applications in the area of multiplierless finite-impulse response (FIR) filters are developed. While the recursive utilization of a common subexpression generates a high logic depth into the digital structure, the NR-SCSE algorithm allows the designer to overcome this problem by using each subexpression once. The paper presents a complete description of the algorithm, and a comparison with two other well-known options: the graph synthesis, and the classical common subexpression elimination technique. Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.

  • 15. Mu, Fenghao
    et al.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Self-tested self-synchronization circuit for mesochronous clocking2001In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 48, no 2, p. 129-140Article in journal (Refereed)
    Abstract [en]

    In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-╡m CMOS. Comparison is made between STSS-1 and STSS-2.

  • 16.
    Wikner, Jacob
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Tan, Nianxiong
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling of CMOS digital-to-analog converters for telecommunication1999In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 46, no 5, p. 489-499Article in journal (Refereed)
    Abstract [en]

    This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling.

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