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  • 1.
    Afzal, Nadeem
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, p. 641-645Article in journal (Refereed)
    Abstract [en]

    In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

  • 2.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed)
    Abstract [en]

    A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

  • 3.
    Angelov, Pavel
    et al.
    AnaCatum Design AB, S-58330 Linkoping, Sweden.
    Ahmed Aamir, Syed
    Heidelberg University, Germany.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 11, p. 860-864Article in journal (Refereed)
    Abstract [en]

    We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.

  • 4.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmailzadeh Najari, Omid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS2013In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

  • 5.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ojani, Amin
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed)
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

  • 6.
    Eghbali, Amir
    et al.
    Thyselius AB, Huawei Technol. Sweden AB, Gothenburg, Sweden.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Design of Modulated Filter Banks and Transmultiplexers With Unified Initial Solutions and Very Few Unknown Parameters2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 4, p. 397-401Article in journal (Refereed)
    Abstract [en]

    This brief proposes a method for designing modulated filter banks (FBs) with a large number of channels. The impulse response of the long prototype filter is parameterized in terms of a few short impulse responses, thus significantly reducing the number of unknown parameters. The proposed method starts by first obtaining an FB with a few channels. The solution of this FB is then partly reused as an initial (very close to final) solution in the design of FBs with a large number of channels. The number of unknown parameters hence drastically reduces. For example, we can first design a cosine modulated FB (CMFB) with three channels whose prototype filter has a stopband attenuation of about 40 dB. We can then reuse the solution of this CMFB in the design of a CMFB with 16 384 channels whose prototype filter has a similar stopband attenuation. With our proposed method, we need to reoptimize only 14 parameters to design the CMFB with 16 384 channels.

  • 7.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jung, Ylva
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Landin, Per Niklas
    Royal Institute of Technology, Sweden.
    Handel, Peter
    Royal Institute of Technology, Sweden.
    Enqvist, Martin
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS2011In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 642-646Article in journal (Refereed)
    Abstract [en]

    This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.

  • 8.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS2012In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 11, p. 726-730Article in journal (Refereed)
    Abstract [en]

    This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and +29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.

  • 9.
    Garrido Gálvez, Mario
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    The Feedforward Short-Time Fourier Transform2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 9, p. 868-872Article in journal (Refereed)
    Abstract [en]

    This brief presents the feedforward short-time Fourier transform (STFT). This new approach is based on reusing the calculations of the STFT at consecutive time instants. This leads to significant savings in hardware components with respect to fast Fourier transform based STFTs. Furthermore, the feedforward STFT does not have the accumulative error of iterative STFT approaches. As a result, the proposed feedforward STFT presents an excellent tradeoff between hardware utilization and performance.

  • 10.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Grajal, Jesus
    University of Politecn Madrid.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Optimum Circuits for Bit Reversal2011In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 657-661Article in journal (Refereed)
    Abstract [en]

    This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.

  • 11.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Grajal, Jesus
    University of Politecn Madrid.
    Accurate Rotations Based on Coefficient Scaling2011In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 662-666Article in journal (Refereed)
    Abstract [en]

    This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.

  • 12.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Huang, Shen-Jui
    Novatek Corp, Taiwan.
    Chen, Sau-Gee
    National Chiao Tung University, Taiwan.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    The Serial Commutator FFT2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 10, p. 974-978Article in journal (Refereed)
    Abstract [en]

    This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.

  • 13.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Källström, Petter
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Kumm, Martin
    University of Kassel, Germany.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    CORDIC II: A New Improved CORDIC Algorithm2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 2, p. 186-190Article in journal (Refereed)
    Abstract [en]

    In this brief, we present the CORDIC II algorithm. Like previous CORDIC algorithms, the CORDIC II calculates rotations by breaking down the rotation angle into a series of microrotations. However, the CORDIC II algorithm uses a novel angle set, different from the angles used in previous CORDIC algorithms. The new angle set provides a faster convergence that reduces the number of adders with respect to previous approaches.

  • 14.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Unnikrishnan, Nanda K.
    Univ Minnesota, MN 55455 USA.
    Parhi, Keshab K.
    Univ Minnesota, MN 55455 USA.
    A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals2018In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, no 11, p. 1693-1697Article in journal (Refereed)
    Abstract [en]

    This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 log(2) N - 2 real adders, log(2) N - 2 real multipliers, and N + 9 log(2) N - 19 real delay elements, where N represents the size of the FFT.

  • 15.
    Garrido, Mario
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal2019In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 66, no 4, p. 657-661Article in journal (Refereed)
    Abstract [en]

    This brief presents novel circuits for calculating the bit reversal on parallel data. The circuits consist of delays/memories and multiplexers, and have the advantage that they requires the minimum number of multiplexers among circuits for parallel bit reversal so far, as well as a small total memory.

  • 16.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Pasha, Muhammad Touqir
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Aliasing-Compensated Polar PWM Transmitter2017In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 64, no 8, p. 912-916Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

  • 17.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, p. 743-747Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 18.
    Jakobsson, Anders
    et al.
    Huawei Technologies Sweden AB, Kista, Sweden.
    Serban, Adriana
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Gong, Shaofang
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    A Low Noise RC-based Phase Interpolator in 16-nm CMOS2019In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 66, no 1Article in journal (Refereed)
    Abstract [en]

    This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm2.

  • 19.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Fractional-Delay and Supersymmetric Mth-Band Linear-Phase FIR Filters Utilizing Partially Symmetric and Antisymmetric Impulse Responses2012In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 6, p. 366-370Article in journal (Refereed)
    Abstract [en]

    This brief considers fractional-delay finite-length impulse response (FIR) filters and a class of supersymmetric Mth-band linear-phase FIR filters utilizing partially symmetric and partially antisymmetric impulse responses. Design examples reveal significant multiplication savings, depending on the specification, as compared to traditional filters.

  • 20.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Goeckler, Heinz
    Ruhr University of Bochum, Germany; Karlsruhe Institute Technology, Germany.
    Two-Stage-Based Polyphase Structures for Arbitrary-Integer Sampling Rate Conversion2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, p. 486-490Article in journal (Refereed)
    Abstract [en]

    This brief derives efficient two-stage-based polyphase structures for arbitrary-integer sampling rate conversion. For even-integer conversions, the overall structures correspond to parallelized conventional two-stage structures, but the derivations in this brief offer further insights when comparing the two cases of odd-and even-integer conversions. For the class of linear-phase finite-length impulse response Mth-band filters, it is then demonstrated through design examples that conversions by odd factors are in fact more efficient than by even factors.

  • 21.
    Kumm, Martin
    et al.
    Univ Kassel, Germany.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Garrido Gálvez, Mario
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Zipf, Peter
    Univ Kassel, Germany.
    Optimal Single Constant Multiplication Using Ternary Adders2018In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, no 7, p. 928-932Article in journal (Refereed)
    Abstract [en]

    The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.

  • 22.
    Mishra, Deepak
    et al.
    Department of Electrical Engineering and Bharti School of Telecommunication, Indian Institute of Technology Delhi, New Delhi 110 016, India.
    De, Swades
    Department of Electrical Engineering and Bharti School of Telecommunication, Indian Institute of Technology Delhi, New Delhi 110 016, India.
    Chowdhury, Kaushik R.
    Department of Electrical and Computer Engi-neering, Northeastern University, Boston, MA 02115 USA.
    Charging time characterization for wireless RF energy transfer2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 4, p. 362-366Article in journal (Refereed)
    Abstract [en]

    Wireless energy transfer to the onboard energy storage element using dedicated radio frequency (RF) energy source has the potential to provide sustained network operations by recharging the sensor nodes on demand. To determine the efficiency of RF energy transfer (RFET), characterization of recharging process is needed. Different from classical capacitor-charging operation, the incident RF waves provide constant power (instead of constant voltage or current) to the storage element, which requires a new theoretical framework for analyzing the charging behavior. This work develops the charging equation for replenishing an energy-depleted storage element by RFET. Since the remaining energy on a sensor node is a random parameter, the RF charging time distribution for a given residual voltage distribution is also derived. The analytical model is validated through hardware experiments and simulations.

  • 23.
    Muralidharan Pillai, Anu Kalidas
    et al.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Prefilter-Based Reconfigurable Reconstructor for Time-Interleaved ADCs With Missing Samples2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 4, p. 392-396Article in journal (Refereed)
    Abstract [en]

    This brief proposes a reconstruction scheme for the compensation of frequency-response mismatch errors at the output of a time-interleaved analog-to-digital converter (TI-ADC) with missing samples. The missing samples are due to sampling instants reserved for estimating the channel mismatch errors in the TI-ADC. Compared with previous solutions, the proposed scheme offers substantially lower computational complexity.

  • 24.
    Pasha, Muhammad Touqir
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Fahim Ul Haque, Muhammad
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. NED Univ Engn and Technol, Pakistan.
    Ahmad, Jahanzeb
    Intel Corp, England.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    An All-Digital PWM Transmitter With Enhanced Phase Resolution2018In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, no 11, p. 1634-1638Article in journal (Refereed)
    Abstract [en]

    An all-digital pulse width modulated (PWM) transmitter using outphasing is proposed. The transmitter uses PWM to encode the amplitude, and outphasing for enhanced phase control. In this way, the phase resolution of the transmitter is doubled. The proposed scheme was implemented using Stratix IV FGPA and class-D PAs fabricated in a 130 nm standard CMOS. From the measurement results, a spectral performance improvement is observed due to the enhanced phase resolution. As compared to an all-digital polar PWM transmitter, the error vector magnitude for proposed transmitter is reduced by 4.1% and the adjacent channel leakage ratio shows an improvement of 5.6 dB for a 1.4 MHz LTE up-link signal for a carrier frequency of 700 MHz at the saturated output power of 25 dBm.

  • 25.
    Qazi, Fahad
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, p. 421-425Article in journal (Refereed)
    Abstract [en]

    In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

  • 26.
    Sheikh, Zaka Ullah
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Linear Programming Design of Coefficient Decimation FIR Filters2012In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 1, p. 60-64Article in journal (Refereed)
    Abstract [en]

    The coefficient decimation technique for reconfigurable FIR filters was recently proposed as a filter structure with low computational complexity. In this brief, we propose to design these filters using linear programming taking all configuration modes into account, instead of only considering the initial reconfiguration mode as in previous works. Minimax solutions with significantly lower approximation errors compared to the straightforward design method in earlier works are obtained. In addition, some new insights that are useful when designing coefficient decimation filters are provided.

  • 27.
    Wang, Yinan
    et al.
    National University of Def Technology, Peoples R China.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Xu, Hui
    National University of Def Technology, Peoples R China.
    Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 3, p. 226-230Article in journal (Refereed)
    Abstract [en]

    Due to channel mismatches in time-interleaved analog-to-digital converters (TIADCs), estimation and compensation methods are required to restore the resolution of the individual converters. Whereas several methods exist for linear mismatches, nonlinearity mismatches have not been widely investigated. This brief presents an adaptive background estimation method for nonlinearity mismatches in two-channel TIADCs. It utilizes a normalized least-mean-square algorithm and assumes slight oversampling as well as a polynomial nonlinearity model that is appropriate when smooth errors dominate. Furthermore, two implementation strategies are proposed to enhance its ability for different applications. The estimation performance of the proposed method is evaluated through behavioral-level simulations.

  • 28.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering. Catena Wireless Elect AB, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 3, p. 244-248Article in journal (Refereed)
    Abstract [en]

    This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

  • 29.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, p. 666-670Article in journal (Refereed)
    Abstract [en]

    This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.

1 - 29 of 29
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