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  • 1.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 4, p. 926-937Article in journal (Refereed)
    Abstract [en]

    In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.

  • 2.
    Buonomo, Antonio
    et al.
    University of Naples 2, Italy .
    Lo Schiavo, Alessandro
    University of Naples 2, Italy .
    Asfandyar Awan, M
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Summair Asghar, Malik
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Peter Kennedy, Michael
    National University of Ireland University of Coll Cork, Ireland .
    A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 12, p. 3126-3135Article in journal (Refereed)
    Abstract [en]

    This paper proposes a simple and effective modification of the conventional divide-by-two injection locked frequency divider (ILFD) with direct-injection aimed at allowing both the divide-by-two and the divide-by-three modes of operation. The proposed circuit does not employ additional inductors as usual in divide-by-three ILFDs, but exploits the combined effect of two independent injection techniques. The resulting locking range for the divide-by-three mode is comparable in size to that for the divide-by-two. Thus, the proposed circuit can be an optimum alternative to existing dividers, due to the flexibility of two division ratios and due to the absence of additional inductors. An intuitive explanation of the locking mechanism underlying this ILFD and a quantitative analysis are provided, allowing one to predict the amplitude and phase of oscillation in the locked mode, as well as the locking range, with approximate closed-form expressions. Measurements on a circuit prototype and results from SPICE simulations demonstrate the effectiveness of the circuit and validate the theoretical model and the resulting formulas.

  • 3.
    Chen, Sau-Gee
    et al.
    National Chiao Tung University, Taiwan.
    Huang, Shen-Jui
    Novatek Corp, Taiwan.
    Garrido Gálvez, Mario
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Jou, Shyh-Jye
    National Chiao Tung University, Taiwan.
    Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 10, p. 2869-2877Article in journal (Refereed)
    Abstract [en]

    This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

  • 4.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Qazi, Fahad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 2, p. 358-370Article in journal (Refereed)
    Abstract [en]

    A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

  • 5.
    Garrido Gálvez, Mario
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    A New Representation of FFT Algorithms Using Triangular Matrices2016In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 63, no 10, p. 1737-1745Article in journal (Refereed)
    Abstract [en]

    In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.

  • 6.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Huang, Shen-Jui
    Novatek Corp, Taiwan.
    Chen, Sau-Gee
    Natl Chiao Tung Univ, Taiwan.
    Feedforward FFT Hardware Architectures Based on Rotator Allocation2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, no 2, p. 581-592Article in journal (Refereed)
    Abstract [en]

    In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.

  • 7.
    Garrido Gálvez, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Qureshi, Fahad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 7, p. 2002-2012Article in journal (Refereed)
    Abstract [en]

    This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to low-complexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way. The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs. Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.

  • 8.
    Garrido, Mario
    et al.
    Department of Signal, Systems and Radiocommuncations, Universidad Politecnica de Madrid, Madrid, Spain.
    Parhi, Keshab. K.
    University of Minnesota, USA.
    Grajal, Jesus
    Department of Signal, Systems and Radiocommuncations, Universidad Politecnica de Madrid, Madrid, Spain.
    A Pipelined FFT Architecture for Real-Valued Signals2009In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 56, no 12, p. 2634-2643Article in journal (Refereed)
    Abstract [en]

    This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.

  • 9.
    Jakobsson, Anders
    et al.
    Huawei Technologies Sweden, Kista, Sweden .
    Grewing, Christian
    Huawei Technologies Sweden, Kista, Sweden .
    Serban, Adriana
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Gong, Shaofang
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Frequency Synthesizer With Dual Loop Frequency and Gain Calibration2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 11, p. 2911-2919Article in journal (Refereed)
    Abstract [en]

    A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 $mu$ m CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain ($K_{rm VCO}$ of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 $mu$s including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is ${-}123$ dBc/Hz and the integrated phase error (1 kHz–2 MHz) is 1.26 $^{circ}$.

  • 10.
    Jakobsson, Anders
    et al.
    Huawei Technol Sweden AB, S-16494 Kista, Sweden.
    Serban, Adriana
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Gong, Shaofang
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS2015In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 3, p. 680-688Article in journal (Refereed)
    Abstract [en]

    A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 um CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.

  • 11.
    Jing Xu, Wei
    et al.
    Nanyang Technology University, Singapore .
    Jun Yu, Ya
    Nanyang Technology University, Singapore .
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 3, p. 764-777Article in journal (Refereed)
    Abstract [en]

    The paper proposes an optimization technique for the design of variable digital filters with simultaneously tunable bandedge and fractional delay using a fast filter bank (FFB) approach. In the FFB approach, full band signals are split into multibands, and each band is multiplied by a proper phase shift to realize the variable fractional delay. In the proposed technique, in the formulation of the optimization of the 0th stage prototype filter of the FFB, the ripples of the filters in the subsequent stages are all taken into consideration. In addition, a shaping filter is applied to the last retained band of the FFB to form the transition band of the variable filter, such that the transition width of each band in the FFB can be relaxed to reduce the computational complexity. In total three shaping filters, constructed from a prototype filter, can be shared by different bands, so that the extra cost incurred due to the shaping filter is low.

  • 12.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Add-Equalize Structures for Linear-Phase Nyquist FIR Filter Interpolators and Decimators2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 6, p. 1766-1777Article in journal (Refereed)
    Abstract [en]

    This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (th-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted -norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures.

  • 13.
    Johansson, Håkan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Eghbali, Amir
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Two Polynomial FIR Filter Structures With Variable Fractional Delay and Phase Shift2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 5, p. 1355-1365Article in journal (Refereed)
    Abstract [en]

    This paper introduces two polynomial finite-length impulse response (FIR) digital filter structures with simultaneously variable fractional delay (VFD) and phase shift (VPS). The structures are reconfigurable (adaptable) online without redesign and do not exhibit transients when the VFD and VPS parameters are altered. The structures can be viewed as generalizations of VFD structures in the sense that they offer a VPS in addition to the regular VFD. The overall filters are composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. A systematic design algorithm, based on iteratively reweighted l(1)- norm minimization, is proposed. It generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails. The paper considers two different structures, referred to as the basic structure and common-subfilters structure, and compares these proposals as well as the existing cascaded VFD and VPS structures, in terms of arithmetic complexity, delay, memory cost, and transients. In general, the common-subfilters structure is superior when all of these aspects are taken into account. Further, the paper shows and exemplifies that the VFDPS filters under consideration can be used for simultaneous resampling and frequency shift of signals.

  • 14.
    Jung, Ylva
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Enqvist, Martin
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 7, p. 1915-1928Article in journal (Refereed)
    Abstract [en]

    This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

  • 15.
    Karlsson, Magnus
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Serban, Adriana
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Östh, Joakim
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Owais, Owais
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Gong, Shaofang
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Frequency Triplexer for Ultra-Wideband Systems (6–9 GHz)2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 3, p. 540-547Article in journal (Refereed)
    Abstract [en]

    A triplexer for ultra-wideband radio implemented entirely with distributed microstrips is presented. The triplexer is composed of a triplex junction network and three bandpass filters. The circuit is integrated in a flex-rigid printed circuit board. Three flat 1 GHz sub-bands in the frequency band 6-9 GHz have been achieved. The group delay variation within each 1 GHz sub-band was measured to be less than 0.4 ns. A good agreement between simulation and measurement was obtained, e.g., less than 0.3 dB difference in the forward transmission in the majority of the frequency band.

  • 16.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 11, p. 3075-3084Article in journal (Refereed)
    Abstract [en]

    Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.

  • 17.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 1, p. 273-282Article in journal (Refereed)
    Abstract [en]

    Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

  • 18.
    Pareschi, Fabio
    et al.
    Univ Ferrara, Italy.
    Lustenberger, Felix
    Boegli Gravures SA, Switzerland.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Cavallaro, Joseph
    Rice Univ, TX 77251 USA.
    Guest Editorial Special Issue on the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017)2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, no 3, p. 857-858Article in journal (Other academic)
    Abstract [en]

    n/a

  • 19.
    Pasha, Muhammad Touqir
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Fahim Ul Haque, Muhammad
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering. NED Univ Engn and Technol, Pakistan.
    Ahmad, Jahanzeb
    Intel Corp, England.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Modified All-Digital Polar PWM Transmitter2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, no 2, p. 758-768Article in journal (Refereed)
    Abstract [en]

    This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.

  • 20.
    Unnikrishnan, Vishnu
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Mitigation of Sampling Errors in VCO-Based ADCs2017In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 64, no 7, p. 1730-1739Article in journal (Refereed)
    Abstract [en]

    Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.

  • 21.
    Unnikrishnan, Vishnu
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Time-Mode Analog-to-Digital Conversion Using Standard Cells2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 12, p. 3348-3357Article in journal (Refereed)
    Abstract [en]

    Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

  • 22.
    Wang, Yinan
    et al.
    National University of Def Technology, Peoples R China.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Xu, Hui
    National University of Def Technology, Peoples R China.
    Sun, Zhaolin
    National University of Def Technology, Peoples R China.
    Joint Blind Calibration for Mixed Mismatches in Two-Channel Time-Interleaved ADCs2015In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 6, p. 1508-1517Article in journal (Refereed)
    Abstract [en]

    To further enhance the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear mismatches should be estimated and compensated for. This paper introduces a method for joint calibration of several types of linear and nonlinear mismatch errors in two-channel TI-ADCs. To demonstrate the generality of this method, we take different scenarios into account, including static and dynamic mixed mismatch models. The proposed method utilizes a normalized least-mean square (N-LMS) algorithm as well as a certain low degree of oversampling for the overall converter to estimate and compensate for the mixed mismatch errors. The calibration performance and computational complexity are investigated and evaluated through simulations.

  • 23.
    Östh, Joakim
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Karlsson, Magnus
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Serban, Adriana
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Gong, Shaofang
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    A Comparative Study of Single-Ended vs. Differential Six-Port Modulators for Wireless Communications2015In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 2, p. 564-570Article in journal (Refereed)
    Abstract [en]

    If present, nonlinear effects in a six-port modulator cause distortion and degradation of the quality of the modulated output waveform. How nonlinear effects occur and their impact on system performance were derived in a mathematical model. The model shows that non-ideal performance of the passive six-port correlator is the main contributor to nonlinear distortion. Simulations and measurements on two manufactured six-port modulators were used to validate the theory and to give deeper insight on system performance. It is shown that by using a differentially signaled six-port modulator instead of a single-ended six-port modulator, better performance is achieved over a wide bandwidth. For an error vector magnitude of less than 10%, the relative bandwidth was measured to 12% for the single-ended but 30% for the differentially signaled modulator

1 - 23 of 23
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