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  • 1.
    Cortes, Luis-Alejandro
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Modeling and formal verification of embedded systems based on a Petri net representation2003In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 49, no 12-15, p. 571-598Article in journal (Refereed)
    Abstract [en]

    In this paper we concentrate on aspects related to modeling and formal verification of embedded systems. First, we define a formal model of computation for embedded systems based on Petri nets that can capture important features of such systems and allows their representation at different levels of granularity. Our modeling formalism has a well-defined semantics so that it supports a precise representation of the system, the use of formal methods to verify its correctness, and the automation of different tasks along the design process. Second, we propose an approach to the problem of formal verification of embedded systems represented in our modeling formalism. We make use of model checking to prove whether certain properties, expressed as temporal logic formulas, hold with respect to the system model. We introduce a systematic procedure to translate our model into timed automata so that it is possible to use available model checking tools. We propose two strategies for improving the verification efficiency, the first by applying correctness-preserving transformations and the second by exploring the degree of parallelism characteristic to the system. Some examples, including a realistic industrial case, demonstrate the efficiency of our approach on practical applications. © 2003 Elsevier B.V. All rights reserved.

  • 2.
    Horga, Adrian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Chattopadhyay, Sudipta
    Centre for IT-Security, Privacy and Accountability, Saarland University, Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Systematic detection of memory related performance bottlenecks in GPGPU programs2016In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 71, p. 73-87Article in journal (Refereed)
    Abstract [en]

    Graphics processing units (GPUs) pose an attractive choice for designing high-performance and energy-efficient software systems. This is because GPUs are capable of executing massively parallel applications. However, the performance of GPUs is limited by the contention in memory subsystems, often resulting in substantial delays and effectively reducing the parallelism. In this paper, we propose GRAB, an automated debugger to aid the development of efficient GPU kernels. GRAB systematically detects, classifies and discovers the root causes of memory-performance bottlenecks in GPUs. We have implemented GRAB and evaluated it with several open-source GPU kernels, including two real-life case studies. We show the usage of GRAB through improvement of GPU kernels on a real NVIDIA Tegra K1 hardware – a widely used GPU for mobile and handheld devices. The guidance obtained from GRAB leads to an overall improvement of up to 64%.

  • 3.
    Jiang, Wei
    et al.
    University of Elect Science and Technology China, Peoples R China.
    Jiang, Ke
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Zhang, Xia
    University of Texas Dallas, TX 75230 USA.
    Ma, Yue
    University of Notre Dame, IN 46556 USA.
    Energy Optimization of Security-Critical Real-Time Applications with Guaranteed Security Protection2015In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 61, no 7, p. 282-292Article in journal (Refereed)
    Abstract [en]

    Designing energy-efficient applications has become of critical importance for embedded systems, especially for battery-powered systems. Additionally, the emerging requirements on both security and real-time make it much more difficult to produce ideal solutions. In this work, we address the emerging scheduling problem existed in the design of secure and energy-efficient real-time embedded systems. The objective is to minimize the system energy consumption subject to security and schedulability constraints. Due to the complexity of the problem, we propose a dynamic programming based approximation approach to find efficient solutions under given constraints. The proposed technique has polynomial time complexity which is half of existing approximation approaches. The efficiency of our algorithm is validated by extensive experiments and a real-life case study. Comparing with other approaches, the proposed approach achieves energy-saving up to 37.6% without violating the real-time and security constraints of the system.

  • 4.
    Lofwenmark, Andreas
    et al.
    Saab Aeronaut, Linkoping, Sweden.
    Nadjm-Tehrani, Simin
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective2018In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 87, p. 1-11Article, review/survey (Refereed)
    Abstract [en]

    With more functionality added to future safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core processors offer a potential that is promising, but they also suffer from two issues that are only recently being addressed in the safety-critical contexts: lack of methods for assuring timing determinism, and higher sensitivity to permanent and transient faults due to shrinking transistor sizes. This paper reviews major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. We consider the classic approach for analyzing the impact of faults in such systems, namely fault injection. The review therefore explores the area in which timing effects are studied when fault injection methods are used. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with fault tolerance techniques. We assess the applicability of the methods to currently available multi-core processors used in avionics. Dark spots on the research map of the integration problem of hardware reliability and timing predictability for multi-core avionics systems are identified.

  • 5.
    Yang, Tianruo
    et al.
    IDA Linköpings Universitet.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Improved Register-Transfer Level Functional Partioning Approach for Testability2000In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 46, no 3, p. 209-223Article in journal (Refereed)
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