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  • 1.
    Aasa, Amanda
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Svennblad, Amanda
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Design of an Automated Test Setup for Power-Controlled Nerve Stimulator Using NFC for Implantable Sensors2021Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Electrical stimulation on nerves is a relatively new area of research and has been proved to speed up recoveryfrom nerve damage. In this work, the efficiency and stability of antennas integrated on printed circuit boards provided by the department of electrical engineering are examined. An automated test bench containing a stepmotor with a slider and an Arduino is created. Different setups were used when measuring on the boards, which resulted in that the largest antenna gave the most stable output despite the distance between transmitterand receiver. The conclusion was that the second best antenna and the smallest one would be suitable as well,and the better choice if it is to be implemented under the skin. A physical setup consisting of LEDs, an Arduino, a computer, and a function generator was created to examinethe voltage control functionality, where colored LEDs were lit depending on the voltage level. The functionality was then implemented in a circuit that in the future shall be integrated on the printed circuit board. To control high voltages a limiter circuit was examined and implemented. The circuit was simulated and tested, with a realization that a feature covering voltage enlargement is needed for the future. 

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  • 2.
    Aghazadeh, S. R.
    et al.
    Univ Politecn Catalunya BarcelonaTech UPC, Spain.
    Martinez-Garcia, H.
    Univ Politecn Catalunya BarcelonaTech UPC, Spain.
    Barajas-Ojeda, E.
    Univ Politecn Catalunya BarcelonaTech UPC, Spain.
    Saberkari, Alireza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 3-5-GHz, 385-540-ps CMOS true time delay element for ultra-wideband antenna arrays2022In: AEU - International Journal of Electronics and Communications, ISSN 1434-8411, E-ISSN 1618-0399, Vol. 149, article id 154175Article in journal (Refereed)
    Abstract [en]

    This paper proposes an all-pass filter-based true time delay (TTD) element covering a 3-5-GHz ultra-wideband (UWB) frequency. The proposed TTD element designed in a standard 0.18-mu m CMOS technology achieves a tunable delay range of 385-540 ps with 6-ps delay steps and maximum 11% absolute delay error over a 3-5-GHz frequency band. It exhibits an average 3.6-4.6-dB noise figure (NF) within the whole bandwidth. A four-channel beamforming receiver realized by the proposed TTD element is designed and examined in this paper, as well. With the maximum delay of 540 ps and 6-ps average delay resolution, a maximum steering angle of +/- 45 degrees with 5 degrees (18 steps) steering resolution is demonstrated for the beamforming receiver with 2-cm antenna spacing.

  • 3.
    Al-Egli, Fares
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Mohamed Moumin, Hassan
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Control, Design, and Implementation of Quasi Z-source Cascaded H-Bridge Inverter2018Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    This report is about control, design and implementation of a low voltage-fed quasi Z-source three-level inverter. The topology has been interesting for photovoltaic-systems due to its ability to boost the incoming voltage without needing an extra switching control. The topology was first simulated in Simulink and later implemented on a full-bridge module to measure the harmonic distortion and estimating the power losses of the inverter. An appropriate control scheme was used to set up a shootthrough and design a three-level inverter. The conclusion for the report is that the quasi Z-source inverter could boost the DC-link voltage in the simulation. But there should be more consideration to the internal resistance of the components for the implementation stage as it gave out a lower output voltage than expected. 

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  • 4.
    Alrashid, Ivan
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Ljudhändelsedetektor med distribueradeLoRa-anslutna akustiska sensorer2021Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Detecting noise levels explains a lot in urban areas such as noise levels, number of shots, and number of collisions. In this project, a sound detector is installed that communicates via LoRa, Long Range when the sound exceeds a threshold value. The sound detector is implemented as a stand-alone module consisting of three existing modules. The modules used in the project include Lopy4 with Expansion Card 3.1, GPS module, and Sound sensor.

    The sound level, battery level, coordinates, date, and time are transferred via LoRa to a gateway and on to The Thing of Network, TTN website, and at the same time data is saved locally in an SD memory card when the sound exceeds a threshold. The threshold can be modified according to the user's wishes. 

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  • 5. Order onlineBuy this publication >>
    Alvbrant, Joakim
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A study on emerging electronics for systems accepting soft errors2016Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Moore’s law has until today mostly relied on shrinkage of the size of the devices inintegrated circuits. However, soon the granularity of the atoms will set a limit together with increased error probability of the devices. How can Moore’s law continue in thefuture? To overcome the increased error rate, we need to introduce redundancy. Applyingmethods from biology may be a way forward, using some of the strategies that transformsan egg into a fetus, but with electronic cells.

    A redundant system is less sensitive to failing components. We define electronic clayas a massive redundancy system of interchangeable and unified subsystems. We show how a mean voter, which is simpler than a majority voter, impact a redundant systemand how optimization can be formalized to minimize the impact of failing subsystems.The performance at given yield can be estimated with a first order model, without the need for Monte-Carlo simulations. The methods are applied and verified on a redundant finite-impulse response filter.

    The elementary circuit behavior of the memristor, ”the missing circuit element”, is investigated for fundamental understanding and how it can be used in applications. Different available simulation models are presented and the linear drift model is simulated with Joglekar-Wolf and Biolek window functions. Driven by a sinusoidal current, the memristor is a frequency dependent component with a cut-off frequency. The memristor can be densely packed and used in structures that both stores and compute in the same circuit, as neurons do. Surrounding circuit has to affect (write) and react (read) to the memristor with the same two terminals.

    We looked at artificial neural network for pattern recognition, but also for self organization in electronic cell array. Finally we look at wireless sensor network and how such system can adopt to the environment. This is also a massive redundant clay-like system.

    Future electronic systems will be massively redundant and adaptive. Moore’s law will continue, not based on shrinking device sizes, but on cheaper, numerous, unified and interchangeable subsystems.

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  • 6.
    Alvbrant, Joakim
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Keshmiri, Vahid
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Transfer Characteristics and Bandwidth Limitation in a Linear-Drift Memristor Model2015In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), IEEE , 2015, p. 332-335Conference paper (Refereed)
    Abstract [en]

    The linear-drift memristor model, suggested by HP Labs a few years ago, is used in this work together with two window functions. From the equations describing the memristor model, the transfer characteristics of a memristor is formulated and analyzed. A first-order estimation of the cut-off frequency is shown, that illustrates the bandwidth limitation of the memristor and how it varies with some of its physical parameters. The design space is elaborated upon and it is shown that the state speed, the variation of the doped and undoped regions of the memristor, is inversely proportional to the physical length, and depth of the device. The transfer characteristics is simulated for Joglekar-Wolf, and Biolek window functions and the results are analyzed. The Joglekar-Wolf window function causes a distinct behavior in the tranfer characteristics at cut-off frequency. The Biolek window function on the other hand gives a smooth state transfer function, at the cost of loosing the one-to-one mapping between charge and state. We also elaborate on the design constraints derived from the transfer characteristics.

  • 7.
    Amgård, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Bergman, Kevin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Efficient Energy Use of FPGA for Underwater Sensor Network2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Operational time is becoming an increasingly important aspect in electronic devices and is also highly relevant in Underwater Acoustic Sensor Networks (UWSN). This thesis contains a study which explores what can be done to de-crease power consumption while maintaining the same functionality of an FPGA inside an underwater sensor-node network. A longer operational time means a more effective system since reconnaissance is one of UWSN’s area of application. The thesis will also cover the implementation of a new sensor-node ‘mode’ which will add new features and increase operational time.

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  • 8.
    Andersson, Jonatan
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Holmberg, Tobias
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    En kompakt testplattform för felsökning och utveckling av portabelt EKG: Användning av Raspberry Pi för att karaktärisera överföringsfunktionen samt undersökning av WCT2021Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    The project takes it start at the interesting phase testing and verification. A prototype has been started for developing of a portable ECG in cooperation between Linköpings university and an earlier bachelor thesis. The prototypes electrical properties need to be tested and verified. The PCB also needs an examination to see if it has been incorrectly designed. The objective for this product is to minimize the distance between the measuring points relative to a 12-lead ECG. A challenging task is to examine what alternative placements or configurations there is of Wilson Central Terminal which can only be done on the upper body.

    A test platform based on the single card computer Raspberry PI has been developed to ensure the systems functionality by sending a known signal into the system. Next phase after the verification was to undergo and investigate the system behavior when the electrodes is placed on a test person.

    The test platform worked well and was able to put light on both the abilities and constraints. It turned out that in some meaning the PCB is not optimally designed. The total bandwidth for the system is limited and cannot fully represent all frequencies that is needed to cover extreme cases and give an exact health check on the heart.

    The instrument is now able to pick up the electric activities with aid from the loose electrodes, that also has been used under the verification. There still is a small amount of noise left on the signal. Before the instrument can be launched to commercial use there remain a few functions to implement. One thing is to double the bandwidth, it should solve the difficulty to detect the higher frequency. It is not necessary, but to completely shrink and copy the original pattern from a larger EKG-measurement the PCB design must be remade. The results from the new pattern appear to be good enough but must be verified from medical view.

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  • 9.
    Andersson, Lotta
    et al.
    Swedish Meteorol and Hydrol Inst, Sweden.
    Wilk, Julie
    Linköping University, Department of Thematic Studies, Tema Environmental Change. Linköping University, Faculty of Arts and Sciences. Linköping University, Centre for Climate Science and Policy Research, CSPR.
    Graham, L. Phil
    Swedish Meteorol and Hydrol Inst, Sweden.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Mokwatlo, Suzan
    Limpopo Dept Agr and Rural Dev, South Africa.
    Petja, Brilliant
    Water Res Commiss, South Africa; Univ Limpopo, South Africa.
    Local early warning systems for drought - Could they add value to nationally disseminated seasonal climate forecasts?2020In: Weather and Climate Extremes, ISSN 2212-0947, Vol. 28, article id UNSP 100241Article in journal (Refereed)
    Abstract [en]

    Limited application and use of forecast information restrict smallholder farmers ability to deal with drought in proactive ways. This paper explores the barriers that impede use and uptake of seasonal climate forecasts (SCF) in two pilot communities in Limpopo Province. Current interpretation, translation and mediation of national SCF to the local context is weak. A local early warning system (EWS) was developed that incorporated hydrological modelled information based on national SCF, locally monitored rainfall and soil moisture by a wireless sensor network, and signs from indigenous climate indicators. We assessed to what degree this local EWS could improve interpretation of SCF and increase understanding and uptake by farmers. Local extension staff and champion farmers were found to play important knowledge brokering roles that could be strengthened to increase trust of SCF. The local EWS provided added value to national SCF by involving community members in local monitoring, enacting knowledge interplay with indigenous knowledge and simplifying and tailoring SCF and hydrological information to the local context. It also helped farmers mentally prepare for upcoming conditions even if many do not currently have the adaptive mindsets, economic resources or pre-conditions to positively respond to SCF information.

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  • 10.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed)
    Abstract [en]

    A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

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  • 11.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs2020In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 55, no 8, p. 2118-2128Article in journal (Refereed)
    Abstract [en]

    This article presents a novel architecture for realizing the synchronized-switch-harvesting-on-capacitors (SSHC) technique used for enhanced energy extraction from piezoelectric transducers. The proposed architecture allows full integration by utilizing the storage capacitor already present in most energy-harvesting systems. A promising circuit implementation of the technique, named multilevel SSHC (ML-SSHC), is proposed as well, and its performance is analyzed theoretically. Based on that, a fully integrated and power-efficient transistor-level design in 0.18-mu m CMOS is presented and fabricated in a prototype chip. When operating at a mechanical excitation frequency of 22 Hz and delivering between 1.51 mu m and 4.82 mu W, the measured increase in extracted power is 7.01x and 6.71x, respectively, relative to an ideal full-bridge rectifier. While the performance is comparable to the state of the art, this is the first implementation allowing full integration at such low frequencies without posing special requirements on the piezoelectric harvester.

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  • 12.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Analysis of the capacitance-based multilevel bias flip rectifier for piezoelectric energy harvesting2019Report (Other academic)
    Abstract [en]

    This report presents the analysis of a novel capacitance-based multilevel bias flip rectifier used to increase the output power from a piezoelectric vibration energy harvesting system. The ideal voltage flipping efficiency is calculated based on the number of levels used followed by an analysis of the power losses caused by the bottom-plate parasitic capacitance of the flying capacitor used to distribute the charge between the levels. Then the time to complete the bias flip is examined and the difference between using either a diode or energy investment is investigated. This analysis is intended to be used for aiding in the design of such a system.

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    Analysis of the capacitance-based multilevel bias flip rectifier for piezoelectric energy harvesting
  • 13.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ring-oscillator-based timing generator for ultralow-power applications2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

  • 14.
    Armgarth, Astrid
    et al.
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering. RISE Res Inst Sweden AB, Sweden.
    Pantzare, Sandra
    RISE Res Inst Sweden AB, Sweden.
    Arven, Patrik
    J2 Holding AB, Sweden.
    Lassnig, Roman
    RISE Res Inst Sweden AB, Sweden.
    Jinno, Hiroaki
    RIKEN, Japan; Univ Tokyo, Japan.
    Gabrielsson, Erik
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Kifle, Yonatan Habteslassie
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Cherian, Dennis
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Arbring Sjöström, Theresia
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Berthou, Gautier
    Res Inst Sweden AB, Sweden.
    Dowling, Jim
    Res Inst Sweden AB, Sweden; KTH Royal Inst Technol, Sweden.
    Someya, Takao
    RIKEN, Japan; Univ Tokyo, Japan.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Gustafsson, Göran
    RISE Res Inst Sweden AB, Sweden.
    Simon, Daniel
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Berggren, Magnus
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    A digital nervous system aiming toward personalized IoT healthcare2021In: Scientific Reports, E-ISSN 2045-2322, Vol. 11, no 1, article id 7757Article in journal (Refereed)
    Abstract [en]

    Body area networks (BANs), cloud computing, and machine learning are platforms that can potentially enable advanced healthcare outside the hospital. By applying distributed sensors and drug delivery devices on/in our body and connecting to such communication and decision-making technology, a system for remote diagnostics and therapy is achieved with additional autoregulation capabilities. Challenges with such autarchic on-body healthcare schemes relate to integrity and safety, and interfacing and transduction of electronic signals into biochemical signals, and vice versa. Here, we report a BAN, comprising flexible on-body organic bioelectronic sensors and actuators utilizing two parallel pathways for communication and decision-making. Data, recorded from strain sensors detecting body motion, are both securely transferred to the cloud for machine learning and improved decision-making, and sent through the body using a secure body-coupled communication protocol to auto-actuate delivery of neurotransmitters, all within seconds. We conclude that both highly stable and accurate sensing-from multiple sensors-are needed to enable robust decision making and limit the frequency of retraining. The holistic platform resembles the self-regulatory properties of the nervous system, i.e., the ability to sense, communicate, decide, and react accordingly, thus operating as a digital nervous system.

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  • 15.
    Arya, Ishan
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Sundaram, Viswanaath
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    A System Study Of Ultrasonic Transceivers For Haptic Applications2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    We are investigating the use of ultrasound in Haptic applications. Initially abrief background of ultrasonic transducers and its characteristics were presented.Then a theoretical research was documented to understand the concepts that govern haptics. This section also discusses the algorithm adopted by various researches to implement haptics in the professional world. Then investigations were made to understand the behavior of ultrasonic transducers and conduct soft-ware simulations to obtain various results. At first simulations were conducted on Field II software. This simulations involved the creation of elements in trans-ducers, transducer’s spatial impulse responses, transducer’s impulse responsein time and frequency domain, effect of adding apodization to the transducers,pulse echo response of the transducers, beam profile variation along the focallength of the transducers. Then a Matlab based GUI was used to study the relationship between number of elements in transducers, the frequency of the input signal and duty cycle variation of the input wave. A concept of phase shift, which explains the time delay generation was also coded in Matlab.

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  • 16.
    Asif, Shahzad
    et al.
    Western Sydney Univ, Australia.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    An RNS Based Modular Multiplier with Reduced Complexity2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

  • 17.
    Asli, Javad Bagheri
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Saberkari, Alireza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Parallel-Path Amplifier for Fast Output Settling2023In: NEWCAS 2023 CONFERENCE PROCEEDINGS, IEEE, 2023Conference paper (Refereed)
    Abstract [en]

    Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE.

  • 18.
    Attrell, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Holmqvist, Mattias
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Utveckling av en kompakt BLE-modul i en portabel EKG: Med möjlighet till kontinuerlig dataöverföring2022Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Electrocardiography or ECG is used in healthcare to measure the electrical activity of the heart using several electrodes that are placed on the body. From the measurements, indications of heart diseases and heart rhythm disorders can be detected and then treated. Cardiovascular disease is the most common cause of death in Sweden and the need for ECG examinations is great. Usually the ECG devices are large, awkward, and limited to hospitals as they are complicated and expensive. Linköping University's research group together with several bachelor thesis projects has developed a prototype of a compact and portable ECG. The portable ECG device is connected to a bra that is integrated with electrodes and should be used mainly by women, as the range of user-friendly ECGs for women is small.

    The previously portable ECG is made up of two modules, the ECG module, and the Nordic Thingy52. The ECG module is designed on a specially adapted circuit board that performs the actual measurement of the electrodes and calculations. It is then paired with Thingy52 which is responsible for the wireless communication to other devices via Bluetooth Low Energy or BLE as it is also called. The BLE module, which included Thingy52 and the modified source code from previous work, managed some wireless communication but was considered too slow and could not handle continuous data transfer.

    From the previous work questions arose as to whether it was possible to further develop the previous BLE module by improving data transfer and introducing more features. The most desired features were to optimize the module's data transfer to become continuous, implement functionality to save measured values as a type of backup and implement a simple digital filter to filter out noise and disturbances of the measured values. In addition to this, a more compact and smaller circuit board for the BLE module would also be developed that would replace the Thingy52.

    The project began with acquiring knowledge and understanding of how existing and additional functions or services work and how they should be implemented. Choices about which components and development environments would be used during the project were determined. The choice resulted in continuing with the previous System-on-chip, SoC nRF52832 from Nordic Semiconductor around which Thingy52 is designed. As a result, existing development boards could be used and the circuit diagram from Thingy52 could be reused for the new circuit diagram. Before the self-created circuit board could be ordered and tested, verification was needed to determine that the selected SoC was capable of continuous data transfer. This could be done on development card nRF52 SDK with the same type of SoC. The verification of the data transfer was more time consuming than had been expected and unfortunately there was no time to order the circuit board and therefore could not be tested in practice. A circuit diagram was nevertheless performed which has smaller dimensions than Thingy52 and contains the desired parts.

    During the development of the BLE function, it was chosen to use Nordic's new development environment as it simplified programming of advanced functions, like BLE. The choice to change the development environment, however, resulted in the previous programming code, which handled configuration and data transfer with the ECG module, having to be converted to a new operating system after Nordic switched to the Zypher operating system. As a result, functions and libraries were not supported or did not exist. After this, the focus shifted to implementing and integrating the storage function with the BLE and ECG functions. The multithreading tool was introduced to perform and optimize the functions of the BLE module. Lack of time meant that only placeholders for future implementation of digital filters could be performed. Based on the test results over the BLE module, it is also difficult to guarantee that the SoC has time to perform filtering of measurement data during the already limited time interval.

    After some problems and many tests, the bachelor thesis project finally resulted in a compact circuit that could replace Thingy52. Also, a BLE module that can perform data transfer with some continuity and at the same time store measurement data to a SD card without affecting the communication with the ECG module or the user interface. The end product also has many opportunities to be expanded in future work.

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  • 19.
    Balachandran, Arvind
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. arvindb316@gmail.com.
    Performance Evaluation of Modular Multilevel Converters for Photovoltaic Systems2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Modular Multilevel Converters (MMCs), over recent years, have gained popularity in high-voltage(HV) and medium-voltage (MV) applications due to their high reliability. Also, with the rapid growth of solar photovoltaics (PV) and energy storage systems, there is a high demand for efficient and reliable power converter solutions. Therefore, due to the seen merits behind MMCs, this thesis assesses their performance for low-voltage (LV) applications. This is accomplished by comparing basic MMC solutions with an equivalent flying capacitors based solution. Such comparison is based on the evaluation of the passive elements requirements, semi-conductor losses, area, voltage, and current stresses, and common-mode voltage. It is worth mentioning that the evaluation is based on utilizing LV MOSFETs. Furthermore, the thesis introduces a modulation scheme for the full-bridge submodule MMC, thus further exploring the different operating regions of the full-bridge based MMC.

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  • 20.
    Banerjee, Saptarshi
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators2020Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. This thesis paper illustrates several designs of output capacitor-less LDO architecture to enhance Power Supply Rejection (PSR) and optimization of the ideas from different literature to achieve the low quiescent current, stability with fast transient response while the input voltage is low over a wide range of load current. Differ-ent types of transistor schematic designs under definite specifications of the LDOs, which are mostly integrated by major components like Error Amplifier (EA) and pass transistor, feedback resistors, and relatively small output capacitor have mostly considered for the designs. However, some buffer attenuation techniques which can improve the PSR have also been shown with a proper diagram. The design of LDOwith the components and how to design the pass device and their trade off’s have been has been discussed. Different techniques of PSR enhancement among which some of the techniques have been implemented have been illustrated with respective diagrams. A study of executed techniques under the specifications with comparative results has been shown with their trade-off with the other architecture. The contribution is an LDO that has been simulated in Cadence specter and designed in CMOS FinFET process node atVdd= 0.95 V with a load current of 50 mA -75 mA and an output voltage of 0.75 V with a small output capacitor of 200 pF, a PSR of−25 dB at 100 MHz has been achieved whereas the current consumption at the load is 245μA, while meeting the targeted stability analysis of gain margin and phase margin of 47 dB and 63◦respectively. A small voltage droop of 36. 6mV for rising edge and−15.99 mV for falling edge over a 100μA to 75 mA step-change in10 ns has been observed.

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  • 21.
    Bengtsson, Johnny
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering. Polismyndigheten - Nationellt forensiskt centrum, Sektionen för informationsteknik.
    Gazmend, Huskaj
    Försvarshögskolan, Militärvetenskapliga institutionen (MVI), Avdelningen för ledningsvetenskap och militärteknik (ALM), Sektionen för militärtekniska system (MteS). Högskolan i Skövde, Institutionen för informationsteknologi.
    The Manifestation of Chinese Strategies Into Offensive Cyberspace Operations Targeting Sweden2021In: Proceedings of the 20th European Conference on Cyber Warfare and Security / [ed] Dr. Thaddeus Eze, Dr. Lee Speakman and Dr. Cyril Onwubiko, Reading, UK: Academic Conferences International Limited , 2021, p. 35-43Conference paper (Refereed)
    Abstract [en]

    The aim of this article is to present how Chinese strategies are manifested into offensive cyberspace operations targeting Sweden. It is commonly known that People’s Republic of China (PRC, and in this definition the meaning of thegovernment and its military), uses five-year plans (FYP) for social and economic steering strategy of their country. This has been going on since 1953 until today. In 2015, the national strategic plan Made in China 2025 (中国制造2025) was launched by Le Keqiang, the Premier of the State Council of PRC. The main goal with this plan is to strengthen the economic development. In addition, Chinese military strategists noted the importance of information warfare and intelligence during military operations. This article is based on open sources: the official English translated version of the 13th Five-year plan (FYP) and other reporting on cyberspace operations linked to the PRC. A number of cases are presented to highlight the link between the PRC FYP and their targets. Next, the current situation in Sweden is presented and how the country is targeted by PRC-linked activities, both in and through cyberspace, but also military infiltration on academia. The results show that Sweden has been, and is continuously the target of offensive cyberspace operations. In parallel, the country is also the target of military infiltration on the academia, and direct investment strategies such as Huawei attempting to compete for the 5G frequency actions arranged by the Swedish Post and Telecom Authority. In conclusion, Sweden will continue to experience cyberespionage from PRC on all levels and on all domains; science, technology, IP and privacy information theft. Previously unveiled cyberspace operations cases in this article have proven to be a convenient strategy for the PRC to reduce its research and development gap in several ways; innovatively, financially and to shortening the time-to-market (TTM).

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  • 22.
    Bengtsson, Richard
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Lindgren, Joel
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Portabel EKG: Med möjlighet att trådlöst överföra och behandla EKG-data2020Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Cardiovascular disease is the most common cause of death in Sweden and if these heart defects can be diagnosed at an early stage, the chance of survival in the sufferer is very high. This project involved designing a modular and portable ECG system that can measure at least seven leads and wirelessly over Bluetooth Low Energy transfer ECG data to a computer or mobile where it can be saved for later analysis. The three modules used in the project are a demonstration board from Texas Instrument, which builds around the analog to digital converter ADS1298 designed to collect ECG data, Nordic Thingy 52 which wirelessly via Bluetooth Low Energy transmits the collected ECG data and a Raspberry Pi for storage and data management. The measured values ​​must be saved in a file that can later be used to visualize an ECG complex. 

    The work began with a feasibility study and a design specification as a basis for the ECG system. When the system was implemented several different ECGs was done to test so that data transfer and filtering were correct. The completed ECG system proved to meet the requirements set at the beginning of the project and has a very high potential for improvement in the future. 

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  • 23.
    Berggren, Magnus
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Simon, Daniel
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Nilsson, D
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Dyreklev, P
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Norberg, P
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Nordlinder, S
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Ersman, PA
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Gustafsson, G
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Hederén, J
    DU Radio, Ericsson AB, SE-583 30, Linköping, Sweden..
    Hentzell, H
    Swedish ICT Research, Box 1151, SE-164 26, Kista, Sweden..
    Browsing the Real World using Organic Electronics, Si-Chips, and a Human Touch.2016In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 28, no 10, p. 1911-1916Article in journal (Refereed)
    Abstract [en]

    Organic electronics have been developed according to an orthodox doctrine advocating "all-printed, "all-organic and "ultra-low-cost primarily targeting various e-paper applications. In order to harvest from the great opportunities afforded with organic electronics potentially operating as communication and sensor outposts within existing and future complex communication infrastructures, high-quality computing and communication protocols must be integrated with the organic electronics. Here, we debate and scrutinize the twinning of the signal-processing capability of traditional integrated silicon chips with organic electronics and sensors, and to use our body as a natural local network with our bare hand as the browser of the physical world. The resulting platform provides a body network, i.e., a personalized web, composed of e-label sensors, bioelectronics, and mobile devices that together make it possible to monitor and record both our ambience and health-status parameters, supported by the ubiquitous mobile network and the resources of the "cloud".

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  • 24.
    Bergman, Kevin
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Amgård, Erik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Wireless Communication Using Energy Harvesting Push Button2016Independent thesis Basic level (degree of Bachelor), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A disadvantage with battery powered circuits is the fact that the battery sometimes can run out of power. If a button that can generate energy by applying mechanical work to it was applied instead of batteries, is it possible to enable a transmitter to stay active long enough to transmit data which can later by received and decoded?

    This thesis contains a study, in which how to effectively send data wirelessly between a transmitter and receiver module, without the use of any batteries or external power sources, only an energy harvesting push button is constructed and evaluated. There will also be a theoretical comparison between different transmission formats and which is more suitable for a task such as this.

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  • 25. Order onlineBuy this publication >>
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters2015Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ΔΣ DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced.

    Achieving a large bandwidth from ΔΣ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ΔΣ DAC architectures, even in nanometer CMOS processes. Time-interleaved ΔΣ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.

    The rst work is an 8-GS/s interleaved ΔΣ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype.

    The performance of a two-channel interleaved ΔΣ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ΔΣ DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented.

    The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ΔΣ DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ΔΣ DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.

    List of papers
    1. An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
    Open this publication in new window or tab >>An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
    2013 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed) Published
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2013
    Keywords
    Digital Delta Sigma modulator (DDSM), digital-to-analog converter (DAC), MASH, oversampling, time interleaving
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-96713 (URN)10.1109/TCSII.2013.2258272 (DOI)000322030600004 ()
    Note

    Funding Agencies|Swedish Foundation for Strategic Research (SSF)||

    Available from: 2013-08-23 Created: 2013-08-23 Last updated: 2019-09-05
    2. Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
    Open this publication in new window or tab >>Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
    2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed) Published
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2015
    Keywords
    Delta-sigma (Delta Sigma) modulator; digital Delta Sigma modulator; digital-to-analog converter (DAC); duty cycle; finite-impulse-response (FIR) filter; time interleaving
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-120215 (URN)10.1109/TCSII.2015.2415691 (DOI)000357126000006 ()
    Note

    Funding Agencies|Swedish Foundation for Strategic Research

    Available from: 2015-07-21 Created: 2015-07-20 Last updated: 2019-09-05
    3. A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS
    Open this publication in new window or tab >>A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS
    2015 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed) Published
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

    Place, publisher, year, edition, pages
    IEEE, 2015
    Keywords
    ΔΣ DAC; 60 GHz radio; High speed; IEEE 80211ad; MASH; WiGig; time-interleaving
    National Category
    Signal Processing Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-120624 (URN)10.1109/JSSC.2015.2460375 (DOI)000362359700008 ()
    Note

    Funding text: Swedish Foundation for Strategic Research (SSF); Swedish Research Council (VR); Swedish Innovation Agency (VINNOVA)

    Available from: 2015-08-19 Created: 2015-08-19 Last updated: 2019-09-05Bibliographically approved
    4. Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators
    Open this publication in new window or tab >>Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators
    2013 (English)In: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

    Place, publisher, year, edition, pages
    IEEE, 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-120304 (URN)10.1109/NORCHIP.2013.6702009 (DOI)978-1-4799-1647-4 (ISBN)
    Conference
    IEEE NORCHIP Conference 2013, 11-12 November, Vilnius , Lithuania
    Available from: 2015-07-27 Created: 2015-07-27 Last updated: 2019-09-05Bibliographically approved
    5. Timing challenges in high-speed interleaved ΔΣ DACs
    Open this publication in new window or tab >>Timing challenges in high-speed interleaved ΔΣ DACs
    2014 (English)In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, p. 46-49Conference paper, Published paper (Refereed)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

    Place, publisher, year, edition, pages
    IEEE, 2014
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-114736 (URN)10.1109/ISICIR.2014.7029513 (DOI)
    Conference
    14th International Symposium on Integrated Circuits (ISIC), 10-12 December, Singapore 2014
    Available from: 2015-03-03 Created: 2015-03-03 Last updated: 2019-09-05Bibliographically approved
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  • 26.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

    Download full text (pdf)
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  • 27.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators2013In: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

    Download full text (pdf)
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  • 28.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Timing challenges in high-speed interleaved ΔΣ DACs2014In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, p. 46-49Conference paper (Refereed)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

  • 29.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ojani, Amin
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed)
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

    Download full text (pdf)
    fulltext
  • 30.
    Biswas, Shampa
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Integrated CMOS Doppler Radar: System Specification & Oscillator Design2016Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis report presents system specification, such as frequency and output power level, and selection topology of an oscillator circuit suitable for a CMOS Integrated Doppler radar application, in order to facilitate short range target detection within 5-15 m range, using a 0.35 μm CMOS process. With this selected CMOS process, the frequency band at 2.45 GHz or 5 GHz, with a maximum output power level of 25 mW (e.i.r.p), is found to be appropriate for the whole system to obtain a good performance. In this thesis work, a Ring VCO with pseudo-differential architecture has been designed and optimised for 2.45 GHz application. However, for 5 GHz application, a differential cross-coupled LC VCO oscillator topology has been suggested and it is so designed that it can be further scaled down to operate at a frequency of 2.45 GHz. The performance of the oscillator circuits has been tested at circuit level and has been presented as simulation results in this report.

    Download full text (pdf)
    fulltext
  • 31.
    Blomgren, Fredrik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Read and Write Circuits for Ferroelectric Memory Using Printed Transistor Technologies2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Printed electronics holds the promise of adding intelligence to disposable objects. Low tem- perature additive manufacturing using low-cost substrates, less complex equipment and fewer processing steps allow drastically reduced cost compared to conventional silicon cir- cuits. Ferroelectric memories is a suitable technology for non-volatile storage in printed circuits. Printed organic thin film transistors can be used for logic. Another approach is to reduce the complexity of silicon manufacturing by substituting as many steps as possible for printed alternatives and substitute silicon wafers for cheaper substrates, one such process is printed dopant polysilicon. This thesis explores the possibility of designing circuits using these two transistor technologies for reading and writing ferroelectric memories. Both gen- eration of the voltage pulses necessary for memory operation from a lower supply voltage and the interpretation of the memory response as one of two states is investigated. It is con- cluded, with some reservations, that such circuitry can be implemented using the polysilicon process. Using organic thin film transistors only the latter functionality is shown, generation of the necessary voltage pulses is not achieved but also not completely precluded. 

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    fulltext
  • 32.
    Cao, Wei
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Saberkari, Alireza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ultra Low Power ASK Demodulator/Manchester Decoder for Biomedical Applications2023In: 2023 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE, NORCAS, IEEE , 2023Conference paper (Refereed)
    Abstract [en]

    This paper involves the design and integration of an ultra-low power consumption Amplitude Shift Keying (ASK) demodulator and a digital Manchester decoder for biomedical applications. The ASK demodulator is based on a common source (CS) self-biased envelope detector (ED) with a double feedback loop, succeeded by a static comparator featuring constant transistor bias with a native transistor. While the digital Manchester decoder performs clock and data recovery. The practical implementation of the work is validated through simulations, executed on a standard 65 nm CMOS technology with a 50 Kbps data rate and a carrier frequency of 570 MHz. The average current drawn from a 2.5 V power supply is less than 800 nA while the circuit operates under RF variations and modulation indices ranging from 13.5% to 100%.

  • 33.
    Carlsson, Erik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Underwater Communications System with Focus on Antenna Design2015Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    In this thesis the possibility of building an underwater communication system usingelectromagnetic waves has been explored. The focus became designing and testingan antenna even if the entire system has been outlined as well. The conclusion isthat using magnetically linked antennas in the near field it is a very real possibilitybut for long EM waves in the far field more testing needs to be done. This isbecause a lack of equipment and facilitates which made it hard to do the realworld testing for this implementation even if it should work in theory.

    Download full text (pdf)
    fulltext
  • 34.
    Celius Zacharek, Daniel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Sundqvist, Filip
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Design of Bidirectional DC/DC Battery Management System for Electrical Yacht2018Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Electrical vehicles are getting more popular as the technology around batteries and electrical motors are catching up to the more common combustion engines. Electrical boats are no exception but there are still a lot of boats using old combustion engines that have a big impact on the environment. This study aims to deepen the understanding of the integration of electrical motors into boats by proposing a design of a system using a bidirectional synchronous buckboost converter. This converter is designed to handle the power transfer in a dual battery application, namely consisting of a 12 V battery and a 48 V battery. The converter includes proposed components, a PCB design, as well as the software that is required for the control of the power transfer. The results show that the converter design meets specification and, when using a test-bench, the software is capable of controlling the converter to achieve constant current and constant voltage in both directions.

    Download full text (pdf)
    Design of Bidirectional DCDC Battery Management System for Electrical Yacht
  • 35. Order onlineBuy this publication >>
    Chen, Kairang
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Energy-Efficient Data Converters for Low-Power Sensors2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energy-harvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxide-semiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications.

    The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-μm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage capacitive charge pump (CCP) is utilized to achieve the gain-stage instead of using the switch capacitor (SC) amplifier. Unity-gain OTAs have been used as the analog buffers to prevent the charge sharing between the CCP stages. The detailed design considerations are given in this work. The prototype ADC, designed and fabricated in a low-cost 0.35-μm CMOS process, achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 μW and 96 μW, respectively. The corresponding Schreier FoM are 166.7 dB and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR > 75 dB up

    to 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    As the low-power sensors might be active only for very short time triggered by an external pulse to acquire the data, the third work is a 14-bit asynchronous two-stage pipelined SAR ADC which has been designed and simulated in 0.18-μm CMOS process. A self-synchronous loop based on an edge detector is utilized to generate an internal clock with variable phase. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Three separate asynchronous clock generators are implemented to create the control signals for two sub-ADCs and the gain-stage between. Aiming to reduce the power consumption of the gain-stage, simple source followers as the analog buffers are implemented in the 3-stage CCP gain-stage. Post-layout simulation results show that the ADC achieves a SNDR of 83.5 dB while consuming 2.39 μW with a sampling rate of 10 kS/s. The corresponding Schreier FoM is 176.7 dB.

    List of papers
    1. Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
    Open this publication in new window or tab >>Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
    2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    Place, publisher, year, edition, pages
    Springer, 2016
    Keywords
    Pipelined SAR ADC; High resolution; OTA; Capacitive DAC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-124472 (URN)10.1007/s10470-015-0648-2 (DOI)000367750900011 ()
    Available from: 2016-02-02 Created: 2016-02-01 Last updated: 2019-09-05Bibliographically approved
    2. A pipelined SAR ADC with gain-stage based on capacitive charge pump
    Open this publication in new window or tab >>A pipelined SAR ADC with gain-stage based on capacitive charge pump
    2017 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    Place, publisher, year, edition, pages
    New York: Springer, 2017
    Keywords
    Capacitive charge pump, OTA, Switch capacitor integrator, Two-stage pipelined SAR ADC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Computer Engineering Software Engineering
    Identifiers
    urn:nbn:se:liu:diva-133228 (URN)10.1007/s10470-016-0872-4 (DOI)000391922200005 ()
    Available from: 2016-12-15 Created: 2016-12-15 Last updated: 2019-09-05Bibliographically approved
    3. Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
    Open this publication in new window or tab >>Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
    2015 (English)In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 496-499Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2015
    Keywords
    High resolution; pipeline; power consumption; successive approximation analog-to-digital; converter; two-stage
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-122623 (URN)10.1109/MIXDES.2015.7208570 (DOI)000364071600094 ()978-8-3635-7806-0 (ISBN)
    Conference
    The22 International Conference “Mixed Design of Integrated Circuits and Systems”(MIXDES), Toruń, Poland, 25-27 June 2015
    Available from: 2015-11-16 Created: 2015-11-12 Last updated: 2019-09-05Bibliographically approved
    4. Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
    Open this publication in new window or tab >>Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
    2016 (English)In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, p. 187-190Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

    Place, publisher, year, edition, pages
    IEEE, 2016
    Keywords
    Capacitive charge pump; successive approximation analog-to-digital converter; power consumption; pipeline; two-stage
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-132104 (URN)10.1109/MIXDES.2016.7529729 (DOI)000383221700035 ()978-8-3635-7808-4 (ISBN)
    Conference
    23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)
    Available from: 2016-10-18 Created: 2016-10-17 Last updated: 2019-09-05
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    Energy-Efficient Data Converters for Low-Power Sensors
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  • 36.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    Download full text (pdf)
    fulltext
  • 37.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Capacitive Charge Pump Gain-stage with Source Follower Buffers for Pipelined SAR ADCs2016In: 2016 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 mu m CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 mu W at a sampling frequency of 10 kHz.

  • 38.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump2016In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, p. 187-190Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

  • 39.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Power Analysis for Two-Stage High Resolution Pipeline SAR ADC2015In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 496-499Conference paper (Refereed)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

  • 40.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed)
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    Download full text (pdf)
    fulltext
  • 41.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Asynchronous Clock Generator for a 14-bit Two-stage Pipelined SAR ADC in 0.18 mu m CMOS2016In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.

  • 42.
    Dahl, Emil
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    MOSFET Packaging for Low Voltage DC/DC Converter: Comparing embedded PCB packaging to newly developed packaging2020Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis studies the options of using PCB embedding bare die power MOSFET and new packaging of MOSFET to increase the power density in a PCB. This is to decrease the winding losses in an isolated DC/DC converter which, according to "Flex Power Modules", can be done by improving the interleaving between the layers of the transformer and/or decreasing the AC loop. To test the MOSFET packaging two layout are made from a reference PCB, one using embedded MOSFET and the other using the new packaging. The leakage induction and winding losses are simulated and if they are lower compared to the reference PCB prototypes are manufactured. The simulated result is that PCB embedded MOSFET decrease the leakage induction but the winding loss is higher. With the new packaging the leakage induction is higher and the winding loss has linear characteristics. Only the PCB with the new MOSFET packaging is made because the MOSFET die gate pad is too small for the PCB manufacturer to make a via connection to it. The PCB is tested that it operates as a DC/DC converter with a 40-60 V input and a 12 V output. The PCB is put on a test board in a wind-tunnel to test its characteristics under different wind speeds, input voltage and loads. The result is that the PCB has a higher efficiency than the reference PCB but it has worse thermal resistance. Further development of the design needs to be made to improve the thermal resistance. Using new packaging is a way to continue the development of power converter with lower efficiency but embedding MOSFET needs a less complicated manufacturing process before there is any widespread usage.

    Download full text (pdf)
    fulltext
  • 43.
    Dai, Jianxing
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Analysis and Design of a High-Frequency RC Oscillator Suitable for Mass Production2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Oscillators are components providing clock signals. They are widely required by low-cost on-chip applications, such as biometric sensors and SoCs. As part of a sensor, a relaxation oscillator is implemented to provide a clock reference. Limited by the sensor application, a clock reference outside the sensor is not desired. An RC implementation of the oscillator has a balanced accuracy performance with low-cost advantage. Hence an RC relaxation oscillator is chosen to provide the clock inside the sensor.

    This thesis proposes a current mode relaxation oscillator to achieve low frequency standard deviation across different supplies, temperatures and process corners. A comparison between a given relaxation oscillator and the proposed design is made as well. All oscillators in this thesis use 0.18 μm technology and 1.8 V nominal supply. The proposed oscillator manages to achieve a frequency standard deviation across all PVT variations less than ±6.5% at 78.4 MHz output frequency with a power dissipation of 461.2 μW. The layout of the oscillator's core area takes up 0.003 mm2.

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  • 44.
    Davidsson, Johannes
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Multi-Purpose CAN Monitor Andsingle-Pair Ethernet Protocol Shift forROV2022Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
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    programvara
  • 45.
    Diwakara, Vinod
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    EMC Pre-Compliance Testing and Development in PCB Design2021Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
    Abstract [en]

    Every electronics product should be electromagnetic compatible and adherence to appropriate standards for commercial success. Solar Bora, situated in Linköping, manufactures off-grid power systems with solar cell systems that deliver a high-power output of 230 VACclean and stable electricity. The energy stored in the batteries must be effectively transferred from DC to AC with the help of an inverter module. The current master’s thesis is about radiated emission testing on the controller printed circuit board which contributes to overall emissions in the inverter. EN-61000-6-3: Generic standards - Emission standards for residential, commercial, and light-industrial environments guide the testing procedure.When there are limited prototype runs and a short time to market, knowing and comprehending how different design factors affect EMC performance is critical. This thesis will look at how different layout design factors impact the converter’s radiated emissions. Radiated emissions testing in the frequency range 30 MHz - 1 GHz are the focus. Based on the findings, appropriate mitigation measures are implemented to minimize radiated emission; Altium Designer used in the new converter layout design. The new converter was put through the same emission test as per standard in the lab to ensure its functioning.

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  • 46.
    Djerv, Robin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Investigation of Light and Ultrasound Injected Signals in Microphones2021Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Voice commanded systems (VCS) have been proved to be vulnerable to signal in- jections mimicking voice commands and explored security flaws in market avail- able products for the time of each respective study. Signal injection caused with the help of amplitude modulated ultrasonic waves (being known as DolphinAt- tacks - DA) were proved to work on several such devices in 2017. In 2019, another study were also successful in achieving signal injections using modulated laser also known as LightCommands (LC). This thesis has investigated the occurring circumstances which enables such injections. Simulations and laboratory trials have shown a thermoacoustic origin enabling LC to be injected and the response differs with respect to microphones physical size. DA utilizes the non-linearity of microphones and more linear microphones have indeed been shown to withstand DAs better and physical parameters have been shown to indicate how DA may be optimized for successful injections. The results have been used to provide ideas on how a VCS system can be designed to be more resilient. 

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  • 47.
    Doddanna, Karthik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Hybrid Coupler for LMBA Input Match Using an Active Inductor2021Independent thesis Advanced level (degree of Master (One Year)), 80 credits / 120 HE creditsStudent thesis
    Abstract [en]

    With the increase in demand for compact and high data rate communication systems, there is a need for high efficiency with modulated signals (PAPR 5-10 dB) for base-station power amplifiers. One of the famous architectures used to achieve this is Doherty architecture. The architecture has recently been extended to the Load Modulated Balanced Amplifier (LMBA) concept, where a separate integrated amplifier generates the control signal for load modulation. Almost all published studies are concerned with discrete "PCB-based" solutions for LMBA. In a recent study [1], the potential of designing an integrated LMBA in 0.18 μm CMOS has been evaluated. The main limitation concerning losses and area comes from the quadrature couplers, consisting of either two or four inductors. Using active inductors in the coupler design may be possible to obtain a more cost-effective solution. However, several aspects must be taken into consideration. One is that the power consumption of the active inductor should not exceed the power loss of the passive inductor. Another one is the ability to handle high power signals (high voltage swing), corresponding to 10-15 dBm at the input of the amplifier. The main objective of this thesis is to implement a hybrid coupler using an active inductor based on the theory of gyrators. The circuits were implemented using TSMC 0.18 μm process. The coupler and the active inductor are designed to operate at 2 GHz centre frequency. The active inductor implemented is considerably linear up to 12 dBm. The coupler has an input reflection coefficient (S11) of -26 dB, the transmission coefficient (S21) of -4.4 dB, and a coupling coefficient (S31) of -2.4 dB. The coupler shows good coupling and isolation characteristics. The phase difference between the through-port and the coupled-port of the coupler is 92°. As a result, when used as a power divider at the input of the power amplifiers, a PAE (Power Added Efficiency) of 63% and output power of 23 dBm is obtained at an input power of 12 dBm.

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  • 48.
    Domènech-Gil, Guillem
    et al.
    Linköping University, Department of Thematic Studies, Tema Environmental Change. Linköping University, Faculty of Arts and Sciences.
    Nguyen, Thanh Duc
    Linköping University, Department of Thematic Studies, Tema Environmental Change. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Eriksson, Jens
    Linköping University, Department of Physics, Chemistry and Biology, Sensor and Actuator Systems. Linköping University, Faculty of Science & Engineering.
    Nilsson Påledal, Sören
    Tekn Verken & Linkoping AB, S-58115 Linkoping, Sweden.
    Puglisi, Donatella
    Linköping University, Department of Physics, Chemistry and Biology, Sensor and Actuator Systems. Linköping University, Faculty of Science & Engineering.
    Bastviken, David
    Linköping University, Department of Thematic Studies, Tema Environmental Change. Linköping University, Faculty of Arts and Sciences.
    Electronic Nose for Improved Environmental Methane Monitoring2024In: Environmental Science and Technology, ISSN 0013-936X, E-ISSN 1520-5851, Vol. 58, p. 352-361Article in journal (Refereed)
    Abstract [en]

    Reducing emissions of the key greenhouse gas methane (CH4) is increasingly highlighted as being important to mitigate climate change. Effective emission reductions require cost-effective ways to measure CH4 to detect sources and verify that mitigation efforts work. We present here a novel approach to measure methane at atmospheric concentrations by means of a low-cost electronic nose strategy where the readings of a few sensors are combined, leading to errors down to 33 ppb and coefficients of determination, R-2, up to 0.91 for in situ measurements. Data from methane, temperature, humidity, and atmospheric pressure sensors were used in customized machine learning models to account for environmental cross-effects and quantify methane in the ppm-ppb range both in indoor and outdoor conditions. The electronic nose strategy was confirmed to be versatile with improved accuracy when more reference data were supplied to the quantification model. Our results pave the way toward the use of networks of low-cost sensor systems for the monitoring of greenhouse gases.

  • 49.
    Doñoro Martín, Julia
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Khaddour Basmaji, Mohamad
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Development of Abstract Microcontroller Peripheral2020Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
  • 50. Order onlineBuy this publication >>
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Efficient Integrated Circuits for Wideband Wireless Transceivers2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II.

    The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2–5.2 dB, out-of-band IIP3 > +17 dBm and blocker P1dB > +5 dBm over a frequency range of 0.5–3 GHz.

    The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging them becomes increasingly challenging. The degradation in performance or the drift from the optimal operation points may cause systems to fail. To prevent this effect and ensure acceptable performance in the presence of process, voltage and temperature variations (PVT), test and calibration of the RF ICs become indispensable. A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is proposed. Gain-boosting and sub-ranging techniques are applied to the detection circuit to increase the gain over the full range of input amplitudes without compromising the input impedance. A technique suitable for on-chip third/second-order intercept  point (IP3/IP2) test by embedded RF detectors is also introduced.

    Part II comprises the design and analysis of high-speed switched-capacitor (SC) DACs for 60-GHz radio transmitters. The digital-to-analog converter (DAC) is one of the fundamental building blocks of transmitters. SC DACs offer several advantages over the current-steering DAC architecture. Specifically, lower capacitor mismatch helps the SC DAC to achieve higher linearity. The switches in the SC DAC are realized by MOS transistors in the triode region which substantially relaxes the voltage headroom requirement. Consequently, SC DACs can be implemented using lower supply voltages in advanced CMOS process nodes compared to their currentsteering counterparts. The first work in Part II analyzes the factors limiting the performance of capacitive pipeline DACs. It is shown that the DAC performance is  limited mainly by the clock feed-through and settling effects in the SC  arrays while the impact of capacitor mismatch and kT/C noise are found to be negligible. Based on this analysis, the second work in Part II proposes the split-segmented SC array DAC to overcome the clock feed-through problem since this topology eliminates pipelined charge propagation. Implemented in 65-nm CMOS, the 12-bit SC DAC achieves a Spurious Free Dynamic Range (SFDR) greater than 44 dB within the input signal bandwidth (BW) of 1 GHz with on-chip memory embedded for digital data generation. Power dissipation is 50 mW from 1.2 V supply. Similar performance is achieved with a lower supply voltage (0.9 V) which shows the scalability of the SC DAC for more advanced CMOS technologies. Furthermore, the proposed SC DAC satisfies the spectral mask of the IEEE 802.11ad WiGig standard with a second-order reconstruction filter and hence it can be used for the 60-GHz radio baseband.

    List of papers
    1. Analysis and design of low noise transconductance amplifier for selective receiver front-end
    Open this publication in new window or tab >>Analysis and design of low noise transconductance amplifier for selective receiver front-end
    2015 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, p. 361-372Article in journal (Refereed) Published
    Abstract [en]

    Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

    Place, publisher, year, edition, pages
    Springer, 2015
    Keywords
    Low-noise transconductance amplifier (LNTA); Highly linear LNA; Wideband LNA; SAW-less receiver; Wideband selective RF front-end
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-122187 (URN)10.1007/s10470-015-0629-5 (DOI)000361984600014 ()
    Available from: 2015-10-26 Created: 2015-10-23 Last updated: 2017-12-01Bibliographically approved
    2. Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
    Open this publication in new window or tab >>Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
    2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, p. 421-425Article in journal (Refereed) Published
    Abstract [en]

    In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

    Keywords
    SAW-less receiver, N-path filter, wideband selective RF front-end
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112879 (URN)10.1109/TCSII.2014.2385213 (DOI)000353636400001 ()
    Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05Bibliographically approved
    3. Wideband RF Detector Design for High Performance On-Chip Test
    Open this publication in new window or tab >>Wideband RF Detector Design for High Performance On-Chip Test
    2012 (English)In: NORCHIP 2012, IEEE , 2012, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.

    Place, publisher, year, edition, pages
    IEEE, 2012
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-86345 (URN)10.1109/NORCHP.2012.6403140 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
    Conference
    IEEE NORCHIP 2012, 12-13 November 2012, Copenhagen, Denmark
    Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2016-01-18
    4. Focused Calibration for Advanced RF Test with Embedded RF Detectors
    Open this publication in new window or tab >>Focused Calibration for Advanced RF Test with Embedded RF Detectors
    2013 (English)In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

    Place, publisher, year, edition, pages
    IEEE, 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-97268 (URN)10.1109/ECCTD.2013.6662259 (DOI)9783000437854 (ISBN)9783000434303 (ISBN)
    Conference
    21st European Conference on Circuit Theory and Design (ECCTD), September 8-12, Dresden, Germany
    Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2016-01-18Bibliographically approved
    5. Design and Analysis of High Speed Capacitive Pipeline DACs
    Open this publication in new window or tab >>Design and Analysis of High Speed Capacitive Pipeline DACs
    2014 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, p. 359-374Article in journal (Refereed) Published
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

    Keywords
    capacitive DAC, high speed DAC, highly linear output driver
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-105516 (URN)10.1007/s10470-014-0350-9 (DOI)000342079400005 ()
    Available from: 2014-03-25 Created: 2014-03-25 Last updated: 2019-09-05
    6. A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS
    Open this publication in new window or tab >>A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS
    (English)Manuscript (preprint) (Other academic)
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Communication Systems
    Identifiers
    urn:nbn:se:liu:diva-124007 (URN)
    Available from: 2016-01-18 Created: 2016-01-18 Last updated: 2019-09-05Bibliographically approved
    7. Tunable Selective Receiver Front-End with Impedance Transformation Filtering
    Open this publication in new window or tab >>Tunable Selective Receiver Front-End with Impedance Transformation Filtering
    2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 5, p. 1071-1093Article in journal (Refereed) Published
    Abstract [en]

    A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is proposed in this paper. To achieve blocker rejection comparable to SAW filters, we use a two stage architecture based on a low noise trans-conductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying (LPV) model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate “back folding” by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept a chip design of a tunable RF front-end using 65 nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB,out of bandIIP3 > +17 dBm and blocker P1dB > +5 dBm over frequency range of 0.5—3 GHz.

    Place, publisher, year, edition, pages
    John Wiley & Sons, 2016
    Keywords
    SAW-less receiver; N-path filter; wideband selective RF front-end
    National Category
    Condensed Matter Physics
    Identifiers
    urn:nbn:se:liu:diva-122701 (URN)10.1002/cta.2125 (DOI)000376206000009 ()
    Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-12-01Bibliographically approved
    8. Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend
    Open this publication in new window or tab >>Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend
    2011 (English)In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 825-828Conference paper, Published paper (Refereed)
    Abstract [en]

    A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 - 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 <; -14 dB while the total power consumption is 3.9 mW for 1.2 V supply.

    Place, publisher, year, edition, pages
    Linköping, Sweden: IEEE conference proceedings, 2011
    Keywords
    Low-noise transconductance amplifier (LNTA), continuous-time ΣΔ RF frontend, high linearity LNA, wideband LNA
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-73028 (URN)10.1109/ECCTD.2011.6043832 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
    Conference
    20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011
    Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2016-01-18Bibliographically approved
    9. Highly linear open-loop output driver design for high speed capacitive DACs
    Open this publication in new window or tab >>Highly linear open-loop output driver design for high speed capacitive DACs
    2013 (English)In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-102930 (URN)10.1109/NORCHIP.2013.6702039 (DOI)9781479916474 (ISBN)
    Conference
    31st Norchip Conference, 11-12 November 2013, Vilnius, Lithuania
    Available from: 2014-01-08 Created: 2014-01-08 Last updated: 2019-09-05Bibliographically approved
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