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  • 1.
    Alvbrant, Joakim
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A study on emerging electronics for systems accepting soft errors2016Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Moore’s law has until today mostly relied on shrinkage of the size of the devices inintegrated circuits. However, soon the granularity of the atoms will set a limit together with increased error probability of the devices. How can Moore’s law continue in thefuture? To overcome the increased error rate, we need to introduce redundancy. Applyingmethods from biology may be a way forward, using some of the strategies that transformsan egg into a fetus, but with electronic cells.

    A redundant system is less sensitive to failing components. We define electronic clayas a massive redundancy system of interchangeable and unified subsystems. We show how a mean voter, which is simpler than a majority voter, impact a redundant systemand how optimization can be formalized to minimize the impact of failing subsystems.The performance at given yield can be estimated with a first order model, without the need for Monte-Carlo simulations. The methods are applied and verified on a redundant finite-impulse response filter.

    The elementary circuit behavior of the memristor, ”the missing circuit element”, is investigated for fundamental understanding and how it can be used in applications. Different available simulation models are presented and the linear drift model is simulated with Joglekar-Wolf and Biolek window functions. Driven by a sinusoidal current, the memristor is a frequency dependent component with a cut-off frequency. The memristor can be densely packed and used in structures that both stores and compute in the same circuit, as neurons do. Surrounding circuit has to affect (write) and react (read) to the memristor with the same two terminals.

    We looked at artificial neural network for pattern recognition, but also for self organization in electronic cell array. Finally we look at wireless sensor network and how such system can adopt to the environment. This is also a massive redundant clay-like system.

    Future electronic systems will be massively redundant and adaptive. Moore’s law will continue, not based on shrinking device sizes, but on cheaper, numerous, unified and interchangeable subsystems.

  • 2.
    Alvbrant, Joakim
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Keshmiri, Vahid
    Linköping University, Department of Electrical Engineering, Information Coding. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Transfer Characteristics and Bandwidth Limitation in a Linear-Drift Memristor Model2015In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), IEEE , 2015, p. 332-335Conference paper (Refereed)
    Abstract [en]

    The linear-drift memristor model, suggested by HP Labs a few years ago, is used in this work together with two window functions. From the equations describing the memristor model, the transfer characteristics of a memristor is formulated and analyzed. A first-order estimation of the cut-off frequency is shown, that illustrates the bandwidth limitation of the memristor and how it varies with some of its physical parameters. The design space is elaborated upon and it is shown that the state speed, the variation of the doped and undoped regions of the memristor, is inversely proportional to the physical length, and depth of the device. The transfer characteristics is simulated for Joglekar-Wolf, and Biolek window functions and the results are analyzed. The Joglekar-Wolf window function causes a distinct behavior in the tranfer characteristics at cut-off frequency. The Biolek window function on the other hand gives a smooth state transfer function, at the cost of loosing the one-to-one mapping between charge and state. We also elaborate on the design constraints derived from the transfer characteristics.

  • 3.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture2014In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 10, p. 773-777Article in journal (Refereed)
    Abstract [en]

    A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.

  • 4.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ring-oscillator-based timing generator for ultralow-power applications2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

  • 5.
    Asif, Shahzad
    et al.
    Western Sydney Univ, Australia.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    An RNS Based Modular Multiplier with Reduced Complexity2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

  • 6.
    Berggren, Magnus
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Simon, Daniel
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Nilsson, D
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Dyreklev, P
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Norberg, P
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Nordlinder, S
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Ersman, PA
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Gustafsson, G
    Acreo Swedish ICT, Box 787, SE-601 17, Norrköping, Sweden..
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Hederén, J
    DU Radio, Ericsson AB, SE-583 30, Linköping, Sweden..
    Hentzell, H
    Swedish ICT Research, Box 1151, SE-164 26, Kista, Sweden..
    Browsing the Real World using Organic Electronics, Si-Chips, and a Human Touch.2016In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 28, no 10, p. 1911-1916Article in journal (Refereed)
    Abstract [en]

    Organic electronics have been developed according to an orthodox doctrine advocating "all-printed, "all-organic and "ultra-low-cost primarily targeting various e-paper applications. In order to harvest from the great opportunities afforded with organic electronics potentially operating as communication and sensor outposts within existing and future complex communication infrastructures, high-quality computing and communication protocols must be integrated with the organic electronics. Here, we debate and scrutinize the twinning of the signal-processing capability of traditional integrated silicon chips with organic electronics and sensors, and to use our body as a natural local network with our bare hand as the browser of the physical world. The resulting platform provides a body network, i.e., a personalized web, composed of e-label sensors, bioelectronics, and mobile devices that together make it possible to monitor and record both our ambience and health-status parameters, supported by the ubiquitous mobile network and the resources of the "cloud".

  • 7.
    Bergman, Kevin
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Amgård, Erik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Wireless Communication Using Energy Harvesting Push Button2016Independent thesis Basic level (degree of Bachelor), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    A disadvantage with battery powered circuits is the fact that the battery sometimes can run out of power. If a button that can generate energy by applying mechanical work to it was applied instead of batteries, is it possible to enable a transmitter to stay active long enough to transmit data which can later by received and decoded?

    This thesis contains a study, in which how to effectively send data wirelessly between a transmitter and receiver module, without the use of any batteries or external power sources, only an energy harvesting push button is constructed and evaluated. There will also be a theoretical comparison between different transmission formats and which is more suitable for a task such as this.

  • 8.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters2015Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ΔΣ DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced.

    Achieving a large bandwidth from ΔΣ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ΔΣ DAC architectures, even in nanometer CMOS processes. Time-interleaved ΔΣ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.

    The rst work is an 8-GS/s interleaved ΔΣ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype.

    The performance of a two-channel interleaved ΔΣ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ΔΣ DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented.

    The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ΔΣ DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ΔΣ DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.

    List of papers
    1. An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
    Open this publication in new window or tab >>An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
    2013 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed) Published
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2013
    Keywords
    Digital Delta Sigma modulator (DDSM), digital-to-analog converter (DAC), MASH, oversampling, time interleaving
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-96713 (URN)10.1109/TCSII.2013.2258272 (DOI)000322030600004 ()
    Note

    Funding Agencies|Swedish Foundation for Strategic Research (SSF)||

    Available from: 2013-08-23 Created: 2013-08-23 Last updated: 2017-12-06
    2. Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
    Open this publication in new window or tab >>Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
    2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed) Published
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2015
    Keywords
    Delta-sigma (Delta Sigma) modulator; digital Delta Sigma modulator; digital-to-analog converter (DAC); duty cycle; finite-impulse-response (FIR) filter; time interleaving
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-120215 (URN)10.1109/TCSII.2015.2415691 (DOI)000357126000006 ()
    Note

    Funding Agencies|Swedish Foundation for Strategic Research

    Available from: 2015-07-21 Created: 2015-07-20 Last updated: 2017-12-04
    3. A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS
    Open this publication in new window or tab >>A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS
    2015 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed) Published
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

    Place, publisher, year, edition, pages
    IEEE, 2015
    Keywords
    ΔΣ DAC; 60 GHz radio; High speed; IEEE 80211ad; MASH; WiGig; time-interleaving
    National Category
    Signal Processing Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-120624 (URN)10.1109/JSSC.2015.2460375 (DOI)000362359700008 ()
    Note

    Funding text: Swedish Foundation for Strategic Research (SSF); Swedish Research Council (VR); Swedish Innovation Agency (VINNOVA)

    Available from: 2015-08-19 Created: 2015-08-19 Last updated: 2018-01-11Bibliographically approved
    4. Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators
    Open this publication in new window or tab >>Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators
    2013 (English)In: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

    Place, publisher, year, edition, pages
    IEEE, 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-120304 (URN)10.1109/NORCHIP.2013.6702009 (DOI)978-1-4799-1647-4 (ISBN)
    Conference
    IEEE NORCHIP Conference 2013, 11-12 November, Vilnius , Lithuania
    Available from: 2015-07-27 Created: 2015-07-27 Last updated: 2015-09-16Bibliographically approved
    5. Timing challenges in high-speed interleaved ΔΣ DACs
    Open this publication in new window or tab >>Timing challenges in high-speed interleaved ΔΣ DACs
    2014 (English)In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, p. 46-49Conference paper, Published paper (Refereed)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

    Place, publisher, year, edition, pages
    IEEE, 2014
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-114736 (URN)10.1109/ISICIR.2014.7029513 (DOI)
    Conference
    14th International Symposium on Integrated Circuits (ISIC), 10-12 December, Singapore 2014
    Available from: 2015-03-03 Created: 2015-03-03 Last updated: 2015-08-19Bibliographically approved
  • 9.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

  • 10.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators2013In: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

  • 11.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Timing challenges in high-speed interleaved ΔΣ DACs2014In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, p. 46-49Conference paper (Refereed)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

  • 12.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ojani, Amin
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed)
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

  • 13.
    Biswas, Shampa
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Integrated CMOS Doppler Radar: System Specification & Oscillator Design2016Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis report presents system specification, such as frequency and output power level, and selection topology of an oscillator circuit suitable for a CMOS Integrated Doppler radar application, in order to facilitate short range target detection within 5-15 m range, using a 0.35 μm CMOS process. With this selected CMOS process, the frequency band at 2.45 GHz or 5 GHz, with a maximum output power level of 25 mW (e.i.r.p), is found to be appropriate for the whole system to obtain a good performance. In this thesis work, a Ring VCO with pseudo-differential architecture has been designed and optimised for 2.45 GHz application. However, for 5 GHz application, a differential cross-coupled LC VCO oscillator topology has been suggested and it is so designed that it can be further scaled down to operate at a frequency of 2.45 GHz. The performance of the oscillator circuits has been tested at circuit level and has been presented as simulation results in this report.

  • 14.
    Blomgren, Fredrik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Read and Write Circuits for Ferroelectric Memory Using Printed Transistor Technologies2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Printed electronics holds the promise of adding intelligence to disposable objects. Low tem- perature additive manufacturing using low-cost substrates, less complex equipment and fewer processing steps allow drastically reduced cost compared to conventional silicon cir- cuits. Ferroelectric memories is a suitable technology for non-volatile storage in printed circuits. Printed organic thin film transistors can be used for logic. Another approach is to reduce the complexity of silicon manufacturing by substituting as many steps as possible for printed alternatives and substitute silicon wafers for cheaper substrates, one such process is printed dopant polysilicon. This thesis explores the possibility of designing circuits using these two transistor technologies for reading and writing ferroelectric memories. Both gen- eration of the voltage pulses necessary for memory operation from a lower supply voltage and the interpretation of the memory response as one of two states is investigated. It is con- cluded, with some reservations, that such circuitry can be implemented using the polysilicon process. Using organic thin film transistors only the latter functionality is shown, generation of the necessary voltage pulses is not achieved but also not completely precluded. 

  • 15.
    Carlsson, Erik
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Underwater Communications System with Focus on Antenna Design2015Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    In this thesis the possibility of building an underwater communication system usingelectromagnetic waves has been explored. The focus became designing and testingan antenna even if the entire system has been outlined as well. The conclusion isthat using magnetically linked antennas in the near field it is a very real possibilitybut for long EM waves in the far field more testing needs to be done. This isbecause a lack of equipment and facilitates which made it hard to do the realworld testing for this implementation even if it should work in theory.

  • 16.
    Chen, Kairang
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Energy-Efficient Data Converters for Low-Power Sensors2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energy-harvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxide-semiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications.

    The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-μm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage capacitive charge pump (CCP) is utilized to achieve the gain-stage instead of using the switch capacitor (SC) amplifier. Unity-gain OTAs have been used as the analog buffers to prevent the charge sharing between the CCP stages. The detailed design considerations are given in this work. The prototype ADC, designed and fabricated in a low-cost 0.35-μm CMOS process, achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 μW and 96 μW, respectively. The corresponding Schreier FoM are 166.7 dB and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR > 75 dB up

    to 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    As the low-power sensors might be active only for very short time triggered by an external pulse to acquire the data, the third work is a 14-bit asynchronous two-stage pipelined SAR ADC which has been designed and simulated in 0.18-μm CMOS process. A self-synchronous loop based on an edge detector is utilized to generate an internal clock with variable phase. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Three separate asynchronous clock generators are implemented to create the control signals for two sub-ADCs and the gain-stage between. Aiming to reduce the power consumption of the gain-stage, simple source followers as the analog buffers are implemented in the 3-stage CCP gain-stage. Post-layout simulation results show that the ADC achieves a SNDR of 83.5 dB while consuming 2.39 μW with a sampling rate of 10 kS/s. The corresponding Schreier FoM is 176.7 dB.

    List of papers
    1. Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
    Open this publication in new window or tab >>Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS
    2016 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

    Place, publisher, year, edition, pages
    Springer, 2016
    Keywords
    Pipelined SAR ADC; High resolution; OTA; Capacitive DAC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-124472 (URN)10.1007/s10470-015-0648-2 (DOI)000367750900011 ()
    Available from: 2016-02-02 Created: 2016-02-01 Last updated: 2017-11-30Bibliographically approved
    2. A pipelined SAR ADC with gain-stage based on capacitive charge pump
    Open this publication in new window or tab >>A pipelined SAR ADC with gain-stage based on capacitive charge pump
    2017 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

    Place, publisher, year, edition, pages
    New York: Springer, 2017
    Keywords
    Capacitive charge pump, OTA, Switch capacitor integrator, Two-stage pipelined SAR ADC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Computer Engineering Software Engineering
    Identifiers
    urn:nbn:se:liu:diva-133228 (URN)10.1007/s10470-016-0872-4 (DOI)000391922200005 ()
    Available from: 2016-12-15 Created: 2016-12-15 Last updated: 2018-01-13Bibliographically approved
    3. Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
    Open this publication in new window or tab >>Power Analysis for Two-Stage High Resolution Pipeline SAR ADC
    2015 (English)In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 496-499Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2015
    Keywords
    High resolution; pipeline; power consumption; successive approximation analog-to-digital; converter; two-stage
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-122623 (URN)10.1109/MIXDES.2015.7208570 (DOI)000364071600094 ()978-8-3635-7806-0 (ISBN)
    Conference
    The22 International Conference “Mixed Design of Integrated Circuits and Systems”(MIXDES), Toruń, Poland, 25-27 June 2015
    Available from: 2015-11-16 Created: 2015-11-12 Last updated: 2016-12-15Bibliographically approved
    4. Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
    Open this publication in new window or tab >>Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
    2016 (English)In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, p. 187-190Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

    Place, publisher, year, edition, pages
    IEEE, 2016
    Keywords
    Capacitive charge pump; successive approximation analog-to-digital converter; power consumption; pipeline; two-stage
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-132104 (URN)10.1109/MIXDES.2016.7529729 (DOI)000383221700035 ()978-8-3635-7808-4 (ISBN)
    Conference
    23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)
    Available from: 2016-10-18 Created: 2016-10-17 Last updated: 2016-12-15
  • 17.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

  • 18.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Capacitive Charge Pump Gain-stage with Source Follower Buffers for Pipelined SAR ADCs2016In: 2016 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 mu m CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 mu W at a sampling frequency of 10 kHz.

  • 19.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump2016In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, p. 187-190Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

  • 20.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Power Analysis for Two-Stage High Resolution Pipeline SAR ADC2015In: Proceedings of the22 International Conference “Mixed Design of Integrated Circuits and Systems”, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 496-499Conference paper (Refereed)
    Abstract [en]

    In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between two-stage pipeline SAR ADC and single SAR ADC is analyzed with the parameters from same technology. The finally results demonstrate that for high resolution ADC design, a particular range is obtained, in which the total power consumption of two-stage pipeline SAR ADC is much lower than single SAR ADC.

  • 21.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed)
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

  • 22.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Asynchronous Clock Generator for a 14-bit Two-stage Pipelined SAR ADC in 0.18 mu m CMOS2016In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.

  • 23.
    Dai, Jianxing
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Analysis and Design of a High-Frequency RC Oscillator Suitable for Mass Production2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Oscillators are components providing clock signals. They are widely required by low-cost on-chip applications, such as biometric sensors and SoCs. As part of a sensor, a relaxation oscillator is implemented to provide a clock reference. Limited by the sensor application, a clock reference outside the sensor is not desired. An RC implementation of the oscillator has a balanced accuracy performance with low-cost advantage. Hence an RC relaxation oscillator is chosen to provide the clock inside the sensor.

    This thesis proposes a current mode relaxation oscillator to achieve low frequency standard deviation across different supplies, temperatures and process corners. A comparison between a given relaxation oscillator and the proposed design is made as well. All oscillators in this thesis use 0.18 μm technology and 1.8 V nominal supply. The proposed oscillator manages to achieve a frequency standard deviation across all PVT variations less than ±6.5% at 78.4 MHz output frequency with a power dissipation of 461.2 μW. The layout of the oscillator's core area takes up 0.003 mm2.

  • 24.
    Duong, Quoc-Tai
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Efficient Integrated Circuits for Wideband Wireless Transceivers2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II.

    The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2–5.2 dB, out-of-band IIP3 > +17 dBm and blocker P1dB > +5 dBm over a frequency range of 0.5–3 GHz.

    The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging them becomes increasingly challenging. The degradation in performance or the drift from the optimal operation points may cause systems to fail. To prevent this effect and ensure acceptable performance in the presence of process, voltage and temperature variations (PVT), test and calibration of the RF ICs become indispensable. A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is proposed. Gain-boosting and sub-ranging techniques are applied to the detection circuit to increase the gain over the full range of input amplitudes without compromising the input impedance. A technique suitable for on-chip third/second-order intercept  point (IP3/IP2) test by embedded RF detectors is also introduced.

    Part II comprises the design and analysis of high-speed switched-capacitor (SC) DACs for 60-GHz radio transmitters. The digital-to-analog converter (DAC) is one of the fundamental building blocks of transmitters. SC DACs offer several advantages over the current-steering DAC architecture. Specifically, lower capacitor mismatch helps the SC DAC to achieve higher linearity. The switches in the SC DAC are realized by MOS transistors in the triode region which substantially relaxes the voltage headroom requirement. Consequently, SC DACs can be implemented using lower supply voltages in advanced CMOS process nodes compared to their currentsteering counterparts. The first work in Part II analyzes the factors limiting the performance of capacitive pipeline DACs. It is shown that the DAC performance is  limited mainly by the clock feed-through and settling effects in the SC  arrays while the impact of capacitor mismatch and kT/C noise are found to be negligible. Based on this analysis, the second work in Part II proposes the split-segmented SC array DAC to overcome the clock feed-through problem since this topology eliminates pipelined charge propagation. Implemented in 65-nm CMOS, the 12-bit SC DAC achieves a Spurious Free Dynamic Range (SFDR) greater than 44 dB within the input signal bandwidth (BW) of 1 GHz with on-chip memory embedded for digital data generation. Power dissipation is 50 mW from 1.2 V supply. Similar performance is achieved with a lower supply voltage (0.9 V) which shows the scalability of the SC DAC for more advanced CMOS technologies. Furthermore, the proposed SC DAC satisfies the spectral mask of the IEEE 802.11ad WiGig standard with a second-order reconstruction filter and hence it can be used for the 60-GHz radio baseband.

    List of papers
    1. Analysis and design of low noise transconductance amplifier for selective receiver front-end
    Open this publication in new window or tab >>Analysis and design of low noise transconductance amplifier for selective receiver front-end
    2015 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, p. 361-372Article in journal (Refereed) Published
    Abstract [en]

    Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

    Place, publisher, year, edition, pages
    Springer, 2015
    Keywords
    Low-noise transconductance amplifier (LNTA); Highly linear LNA; Wideband LNA; SAW-less receiver; Wideband selective RF front-end
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-122187 (URN)10.1007/s10470-015-0629-5 (DOI)000361984600014 ()
    Available from: 2015-10-26 Created: 2015-10-23 Last updated: 2017-12-01Bibliographically approved
    2. Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
    Open this publication in new window or tab >>Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
    2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, p. 421-425Article in journal (Refereed) Published
    Abstract [en]

    In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

    Keywords
    SAW-less receiver, N-path filter, wideband selective RF front-end
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-112879 (URN)10.1109/TCSII.2014.2385213 (DOI)000353636400001 ()
    Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05Bibliographically approved
    3. Wideband RF Detector Design for High Performance On-Chip Test
    Open this publication in new window or tab >>Wideband RF Detector Design for High Performance On-Chip Test
    2012 (English)In: NORCHIP 2012, IEEE , 2012, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.

    Place, publisher, year, edition, pages
    IEEE, 2012
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-86345 (URN)10.1109/NORCHP.2012.6403140 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
    Conference
    IEEE NORCHIP 2012, 12-13 November 2012, Copenhagen, Denmark
    Available from: 2012-12-13 Created: 2012-12-13 Last updated: 2016-01-18
    4. Focused Calibration for Advanced RF Test with Embedded RF Detectors
    Open this publication in new window or tab >>Focused Calibration for Advanced RF Test with Embedded RF Detectors
    2013 (English)In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

    Place, publisher, year, edition, pages
    IEEE, 2013
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-97268 (URN)10.1109/ECCTD.2013.6662259 (DOI)9783000437854 (ISBN)9783000434303 (ISBN)
    Conference
    21st European Conference on Circuit Theory and Design (ECCTD), September 8-12, Dresden, Germany
    Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2016-01-18Bibliographically approved
    5. Design and Analysis of High Speed Capacitive Pipeline DACs
    Open this publication in new window or tab >>Design and Analysis of High Speed Capacitive Pipeline DACs
    2014 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, p. 359-374Article in journal (Refereed) Published
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

    Keywords
    capacitive DAC, high speed DAC, highly linear output driver
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-105516 (URN)10.1007/s10470-014-0350-9 (DOI)000342079400005 ()
    Available from: 2014-03-25 Created: 2014-03-25 Last updated: 2017-12-05
    6. A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS
    Open this publication in new window or tab >>A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS
    (English)Manuscript (preprint) (Other academic)
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Communication Systems
    Identifiers
    urn:nbn:se:liu:diva-124007 (URN)
    Available from: 2016-01-18 Created: 2016-01-18 Last updated: 2016-01-18Bibliographically approved
    7. Tunable Selective Receiver Front-End with Impedance Transformation Filtering
    Open this publication in new window or tab >>Tunable Selective Receiver Front-End with Impedance Transformation Filtering
    2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 5, p. 1071-1093Article in journal (Refereed) Published
    Abstract [en]

    A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is proposed in this paper. To achieve blocker rejection comparable to SAW filters, we use a two stage architecture based on a low noise trans-conductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying (LPV) model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate “back folding” by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept a chip design of a tunable RF front-end using 65 nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB,out of bandIIP3 > +17 dBm and blocker P1dB > +5 dBm over frequency range of 0.5—3 GHz.

    Place, publisher, year, edition, pages
    John Wiley & Sons, 2016
    Keywords
    SAW-less receiver; N-path filter; wideband selective RF front-end
    National Category
    Condensed Matter Physics
    Identifiers
    urn:nbn:se:liu:diva-122701 (URN)10.1002/cta.2125 (DOI)000376206000009 ()
    Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-12-01Bibliographically approved
    8. Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend
    Open this publication in new window or tab >>Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend
    2011 (English)In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 825-828Conference paper, Published paper (Refereed)
    Abstract [en]

    A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 - 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 <; -14 dB while the total power consumption is 3.9 mW for 1.2 V supply.

    Place, publisher, year, edition, pages
    Linköping, Sweden: IEEE conference proceedings, 2011
    Keywords
    Low-noise transconductance amplifier (LNTA), continuous-time ΣΔ RF frontend, high linearity LNA, wideband LNA
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-73028 (URN)10.1109/ECCTD.2011.6043832 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
    Conference
    20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011
    Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2016-01-18Bibliographically approved
    9. Highly linear open-loop output driver design for high speed capacitive DACs
    Open this publication in new window or tab >>Highly linear open-loop output driver design for high speed capacitive DACs
    2013 (English)In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-102930 (URN)10.1109/NORCHIP.2013.6702039 (DOI)9781479916474 (ISBN)
    Conference
    31st Norchip Conference, 11-12 November 2013, Vilnius, Lithuania
    Available from: 2014-01-08 Created: 2014-01-08 Last updated: 2016-01-18Bibliographically approved
  • 25.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Low Noise Linear and Wideband Transconductance Amplifier Design for Current-mode Frontend2014Conference paper (Refereed)
    Abstract [en]

    A low-noise transconductance amplifier (LNTA) aimed at current-mode (Saw-less, Software-define radio) wideband receiver frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient G<;sub>m<;/sub> gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65 nm CMOS, achieves in simulation the noise figure in range [1-1.34] dB and linearity of maximum IIP3 = 16.5 dBm over 0.5-6 GHz band. The maximum transconductance G<;sub>m<;/sub> = 12.9 mS, the return loss S11 <; -10 dB while the total power consumption is 4 mW for 1.2 V supply.

  • 26.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOSManuscript (preprint) (Other academic)
  • 27.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design and analysis of high-speed split-segmented switched-capacitor DACs2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 92, no 2, p. 199-217Article in journal (Refereed)
    Abstract [en]

    In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (WCu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

  • 28.
    Feysal, Hamza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Modell av ett flygplans elektriska system2016Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [sv]

    Målet med projektet var att sammanställa en enkel och optimal modell av ett elsystem för elektrisk kraftförsörjning av olika delsystem och deras apparater genom användande av ett verktyg som kan beräkna spänningsfall i elledningar i flygplan. Modellen ska tjänstgöra som ett verktyg/hjälpmedel vid dimensionering/kontroll av elledningar och säkringar samt snabbt ge besked om huruvida nya laster på kraftbussarna kan ställa till med problem. Detta examensarbete har utförts på Saab Aeronautics och gav ett tillfredställande resultat. 

  • 29.
    Fredriksson, Axel
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Konstruktion av en solcellssimulator2017Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [sv]

    I denna rapport så genomförs en konstruktion av en solpanelkrets. Denna krets kommer att användas i utbildningssyfte så en användare kan skaffa sig en förståelse för hur en solpanel fungerar. Solpanelkretsen seriekopplas för att efterlikna riktiga solpaneler. På kretsen så kan en användare ställa in önskad skuggning som motsvarar olika väderförhållanden som en riktig solpanel kan befinna sig i, samt se hur skugga påverkar en solpanel och seriekopplade solpaneler. Kretsen styrs sedan med någon heter MPPT för att utvinna maximal effekt under alla väderförhållanden som en solpanel kan befinna sig i.

    I rapporten så presenteras först väsentlig solteori för att ge upphov till en ökad förståelse för hur solpaneler fungerar. Rapporten bygger mycket på att jämföra simulerade grafer från kretssimuleringsprogrammet Multisim med den fysiska byggda kretsen. Grafer från en solpanel och seriekopplade solpaneler med och utan bypass dioder presenteras. Mätningar från MPPT-styrningen genomförs för att visa vilken maximal effekt som utvanns från den fysiska byggda kretsen. Alla mätningar som genomförts finns i ett resultatkapitel och till sist så diskuteras resultatet och förslag på vidareutvecklingar.

  • 30.
    Haider, Daniyal
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    On-Chip Phase Measurement Design Study in 65nm CMOS Technology2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.

  • 31.
    Hanson, Maryam
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Study on Smart Dust Networks2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis work is done for the department of Electronic System at The Institute of Technology at Linköping University (Linköpings Tekniska Högskolan). Study's focus is to design and implement a protocol for smart dust networks to improve the energy consumption algorithm for this kind of network.

    Smart dust networks are in category of distributed sensor networks and power consumption is one of the key concerns for this type of network. This work shows that by focusing on improving the algorithmic behavior of power consumption in every network element (so called as mote), we can save a considerable amount of power for the whole network.

    Suggested algorithm is examined using Erlang for one mote object and the whole idea has put into test for a small network using SystemC.

  • 32.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Combined RF and multilevel PWM switch mode power amplifier2013Conference paper (Refereed)
  • 33.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Combined RF and Multiphase PWM Transmitter2015In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 264-267Conference paper (Refereed)
    Abstract [en]

    This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.

  • 34.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Combined RF and Multiphase PWM Transmitter2015Conference paper (Other academic)
  • 35.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Modified Band-limited Pulse-Width Modulated Polar Transmitter2015Conference paper (Other academic)
  • 36.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Modified Multilevel PWM switch mode power amplifier2014Conference paper (Other (popular science, discussion, etc.))
  • 37. Haque, Muhammad Fahim Ul
    et al.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Modified Multilevel PWM Switch Mode Power Amplifier2014Conference paper (Refereed)
  • 38.
    Haque, Muhammad Fahim Ul
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Pasha, Muhammad Touqir
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Aliasing-Compensated Polar PWM Transmitter2017In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 64, no 8, p. 912-916Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

  • 39.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.

    The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2.

    The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

    The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.

    List of papers
    1. A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
    Open this publication in new window or tab >>A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
    2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, p. 743-747Article in journal (Refereed) Published
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2016
    Keywords
    Analog-to-digital converter, ADC, successive approximation register, SAR, ultra-low-voltage
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-122729 (URN)10.1109/TCSII.2016.2531099 (DOI)000381440000007 ()978-1-4799-9877-7 (ISBN)
    Note

    At the time for thesis presentation publication was in status: Manuscript

    Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2017-12-01Bibliographically approved
    2. A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
    Open this publication in new window or tab >>A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
    2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 28-38Article in journal (Refereed) Published
    Abstract [en]

    This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

    Place, publisher, year, edition, pages
    Elsevier, 2015
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-111957 (URN)10.1016/j.vlsi.2015.01.002 (DOI)000357054300003 ()
    Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2017-12-05Bibliographically approved
    3. Design of a Sampling Switch for a 0.4-V SAR ADC Using a Multi-Stage Charge Pump
    Open this publication in new window or tab >>Design of a Sampling Switch for a 0.4-V SAR ADC Using a Multi-Stage Charge Pump
    2014 (English)In: NORCHIP 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.

    Place, publisher, year, edition, pages
    IEEE, 2014
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-114725 (URN)10.1109/NORCHIP.2014.7004703 (DOI)
    Conference
    32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland
    Available from: 2015-03-03 Created: 2015-03-03 Last updated: 2015-11-18Bibliographically approved
    4. Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
    Open this publication in new window or tab >>Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
    2015 (English)In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE , 2015, p. 249-252Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

    Place, publisher, year, edition, pages
    IEEE, 2015
    Series
    IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
    Keywords
    CMOS digital integrated circuits;analogue-digital conversion;buffer circuits;digital-analogue conversion;flip-flops;printed circuits;reference circuits;CMOS;DAC;ENOB;FoM;PCB trace;PSRR performance;RVBuffer;SAR ADC;analog-to-digital converter;bondwire;complementary metal oxide semiconductor;digital-to-analog converter;effective number of bits;energy efficiency;figure of merit;near-Nyquist input;parasitic inductance;post-layout simulation;power 697 muW;power supply rejection ratio;reference voltage buffer;sampling frequency;settling-time noise;size 65 nm;successive approximation register;voltage 1.2 V;word length 10 bit;Capacitors;Clocks;Gain;Inductance;Noise;Power demand;System-on-chip
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-122731 (URN)10.1109/ISCAS.2015.7168617 (DOI)000371471000062 ()
    Conference
    2015 IEEE International Symposium on Circuits and Systems (ISCAS), Date 24-27 May, Lisbon, Portugal
    Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-04-07
    5. A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
    Open this publication in new window or tab >>A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
    2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 13-16Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

    Place, publisher, year, edition, pages
    IEEE, 2015
    Keywords
    CMOS integrated circuits;analogue-digital conversion;mixed analogue-digital integrated circuits;operational amplifiers;silicon-on-insulator;PGA;SAR ADC;Si;UTBB FDSOI CMOS process;analog-mixed-signal circuits;continuous-time CMFB circuits;frequency 4.3 MHz;fully-differential OTA;gain 6 dB;gain 70 dB;operational transconductance amplifier;power 2.9 muW;programmable gain amplifier;reverse body bias;size 28 nm;temperature -20 degC to 85 degC;time 5.8 mus;ultrathin box and body fully-depleted silicon-on-insulator;voltage 1 V;word length 9 bit;Electronics packaging;Gain;Linearity;MOS devices;Resistors;Threshold voltage;Transistors
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-122727 (URN)10.1109/ECCTD.2015.7300114 (DOI)000380498200096 ()978-1-4799-9877-7 (ISBN)
    Conference
    2015 European Conference on Circuit Theory and Design (ECCTD), August 24-26, Trondheim, Norway
    Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-25Bibliographically approved
    6. An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias
    Open this publication in new window or tab >>An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias
    2015 (English)In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

    Place, publisher, year, edition, pages
    IEEE, 2015
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-122728 (URN)10.1109/NORCHIP.2015.7364416 (DOI)000380441400063 ()978-1-4673-6576-5 (ISBN)
    Conference
    2015 NORCAS conference, IEEE Nordic Circuits and Systems Conference, 26-28 October, Oslo, Norway
    Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2016-09-16Bibliographically approved
    7. Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
    Open this publication in new window or tab >>Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
    2014 (English)In: Mixed Design of Integrated Circuits and Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Poland, 2014, p. 185-188Conference paper, Published paper (Refereed)
    Abstract [en]

    The paper presents the design of a single-ended amplifier in 1.8~V, 180 nm CMOS process forbuffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffersuch as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation  achieves worst-case settling time of 19.3~ns andcurrent consumption of 66~$\mu$A while occupying an area of (19.2~$\mu$m $\times$ 19.2~$\mu$m).

    Place, publisher, year, edition, pages
    Poland: , 2014
    Keywords
    SAR ADC, Reference voltage buffer, DAC
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-106913 (URN)10.1109/MIXDES.2014.6872182 (DOI)000345852100036 ()2-s2.0-84906699621 (Scopus ID)978-83-63578-04-6 (ISBN)
    Conference
    21st International Conference, Mixed Design of Integrated Circuits and Systems (MIXDES 2014), June 19-21, 2014, Lublin, Poland
    Available from: 2014-05-26 Created: 2014-05-26 Last updated: 2015-11-18
    8. Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
    Open this publication in new window or tab >>Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
    2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, p. 381-384Conference paper, Oral presentation only (Refereed)
    Abstract [en]

    This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

    Place, publisher, year, edition, pages
    IEEE conference proceedings, 2013
    Series
    International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-87996 (URN)10.1109/ISCAS.2013.6571860 (DOI)000332006800094 ()978-1-4673-5760-9 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
    Available from: 2013-01-28 Created: 2013-01-28 Last updated: 2015-11-18
    9. An Analog Receiver Front-End for Capacitive Body-Coupled Communication
    Open this publication in new window or tab >>An Analog Receiver Front-End for Capacitive Body-Coupled Communication
    2012 (English)In: NORCHIP, 2012, IEEE , 2012, p. 1-4Conference paper, Poster (with or without abstract) (Other academic)
    Abstract [en]

    This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

    Place, publisher, year, edition, pages
    IEEE, 2012
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-84302 (URN)10.1109/NORCHP.2012.6403137 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
    Conference
    30th Norchip Conference 2012, The Nordic Microelectronics event, 12-13 November 2012, Copenhagen, Denmark
    Available from: 2012-10-04 Created: 2012-10-04 Last updated: 2015-11-26Bibliographically approved
  • 40.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology. AnaCatum AB, Linköping, Sweden.
    Angelov, Pavel
    AnaCatum AB, Linköping, Sweden.
    Hägglund, Robert
    AnaCatum AB, Linköping, Sweden.
    Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC2014In: Mixed Design of Integrated Circuits and Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Poland, 2014, p. 185-188Conference paper (Refereed)
    Abstract [en]

    The paper presents the design of a single-ended amplifier in 1.8~V, 180 nm CMOS process forbuffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffersuch as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation  achieves worst-case settling time of 19.3~ns andcurrent consumption of 66~$\mu$A while occupying an area of (19.2~$\mu$m $\times$ 19.2~$\mu$m).

  • 41.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS2015In: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE , 2015, p. 249-252Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

  • 42.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Design of a Sampling Switch for a 0.4-V SAR ADC Using a Multi-Stage Charge Pump2014In: NORCHIP 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.

  • 43.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications2016In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 8, p. 743-747Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.

  • 44.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications2015In: 2015 European Conference on Circuit Theory and Design (ECCTD), IEEE , 2015, p. 13-16Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

  • 45.
    Harikumar, Prakash
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    An Ultra-Low-Voltage OTA in 28 nm UTBB FDSOI CMOS Using Forward Body Bias2015In: Proc. IEEE Nordic Circuits and Systems Conf. (NORCAS), Oslo, Norway, pp. 1-4, Oct. 2015, IEEE , 2015, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

  • 46.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Dehghani, Rasoul
    Isfahan University of Technology, Iran.
    Jalili, Armin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A highly sensitive, low-power, and wide dynamic range CMOS digital pixel sensor2015In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 236, p. 82-91Article in journal (Refereed)
    Abstract [en]

    This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 x 16 DPS with pixel size of 23 x 23 mu m(2) and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images. (C) 2015 Elsevier B.V. All rights reserved.

  • 47.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Dehghani, Rasoul
    Isfahan University of Technology, Iran.
    Jalili, Armin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A low-power wide tuning-range CMOS current-controlled oscillator2016In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 55, p. 57-66Article in journal (Refereed)
    Abstract [en]

    This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 mu A, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 my. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8 x 11.5 mu m(2). (C) 2016 Elsevier B.V. All rights reserved.

  • 48.
    Hassanli, Kourosh
    et al.
    Isfahan University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A compact, low-power, and fast pulse-width modulation based digital pixel sensor with no bias circuit2016In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 244, p. 243-251Article in journal (Refereed)
    Abstract [en]

    A high-speed and compact in-pixel light-to-time converter (LTC), with low power consumption and wide dynamic range is presented. By using the proposed LTC, a digital pixel sensor (DPS) based on a pulse width modulation (PWM) scheme has been designed and fabricated in a standard 180-nm, single-poly, six-metal complementary metal oxide semiconductor (CMOS) technology. The prototype chip consists of a 16 x 16 pixel array with an individual pixel size of 21 x 21 mu m(2) and a fill factor of 39% in the 180-nm CMOS technology. Experimental results show that the circuit operates at supply voltages down to 800 mV and achieves an overall dynamic range of more than 140 dB. The power consumption at 800 mV supply and room light intensity is approximately 2.85 nW. (C) 2016 Elsevier B.V. All rights reserved.

  • 49.
    Hassanli, Kourosh
    et al.
    Shiraz University of Technology, Iran.
    Masoud Sayedi, Sayed
    Isfahan University of Technology, Iran.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    High Resolution Digital Imager Based on Time Multiplexing Algorithm2017In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 17, no 9, p. 2831-2840Article in journal (Refereed)
    Abstract [en]

    In this paper, a new high-resolution digital imager based on a time multiplexing scheme is proposed. The imager produces a 256-grayscale image through capturing 256 successive frames that each belongs to a specific luminance range. Each pixel includes a 1-b analog-to-digital converter (ADC) and a single bit static memory to improve the fill factor. The in-pixel ADC is designed as a compact and fast converter to achieve a high-resolution and video-rate image sensor. The proposed sensor is designed and implemented in a standard 180-nm CMOS technology. The imager achieves an overall dynamic range of over 140 dB at video rate imaging. The pixel pitch is 18.3 mu m and the fill factor is about 48%. The circuit operates at a supply voltage as low as 800 mV. At this supply voltage and at video rate imaging, its power consumption is about 4.33 nW. The proposed imager can directly perform some pre-processing algorithms, such as image segmentation and binarization. Additionally, the proposed method transfers the memory and process units of the pixels to the external of the sensor array so it provides a suitable structure for designing high-resolution, wide dynamic range, and fast general-purpose image sensors.

  • 50.
    He, Zhongxia
    et al.
    Chalmers, Sweden.
    Chen, Jingjing
    Chalmers, Sweden; Ericsson AB, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Bao, Lei
    Ericsson AB, Sweden.
    Rhodin, Anna
    Ericsson AB, Sweden.
    Li, Yinggang
    Ericsson AB, Sweden.
    An, Jianping
    Beijing Institute Technology, Peoples R China.
    Zirath, Herbert
    Chalmers, Sweden; Ericsson AB, Sweden.
    A Hardware Efficient Implementation of a Digital Baseband Receiver for High-Capacity Millimeter-Wave Radios2015In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 63, no 5, p. 1683-1692Article in journal (Refereed)
    Abstract [en]

    This paper presents an implementation solution for a digital baseband receiver, which consists mainly of an analog symbol timing recovery (STR) block and a digital carrier recovery block. The STR is realized based on "one-sample-per-symbol" sampling, resulting in relaxed requirement on the A/D converters sampling speed. In this sense, the proposed implementation solution is hardware efficient. To functionally verify the solution, a proof-of-concept E-band link system is implemented and tested in the laboratory, which supports 5-Gbit/s data traffic using 16 quadrature amplitude modulation. The test results demonstrate that the proposed solution works for high-capacity millimeter-wave radios for point-to-point links, one of the targeted applications.

123 1 - 50 of 121
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