liu.seSearch for publications in DiVA
Change search
Refine search result
1234567 1 - 50 of 510
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the 'Create feeds' function.
  • 1.
    Afghari, Kamran
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Study and Design of High Performance Voltage-Controlled Oscillators in 65nm CMOS Technology2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In recent years, oscillators are considered as inevitable blocks in many electronic systems. They are commonly used in digital circuits to provide clocking and in analog/RF circuits of communication transceivers to support frequency conversion. Nowadays, CMOS technology is the most applicable solution for VLSI and especially for modern integrated circuits used in wireless communications. The main purpose of this project is to design a high performance voltage-controlled oscillator (LC VCO) using 65nm CMOS technology. To meet the state-of-the-art requirements, several circuit solutions have been explored and the design work ended-up with a Quadrature VCO. The circuit operates at center frequency of 2.4 GHz. The phase noise of QVCO obtained by simulation is -140 dBc/Hz at 1MHz offset frequency which is 6 dB less compared to conventional LC VCOs. The power consumption is 3.6mW and the tuning voltage can be swept from 0.2 V to 1.2 V resulting in 2.25 GHz - 2.55 GHz frequency range.

  • 2.
    Ahmad, Shakeel
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Stimuli Generation Techniques for On-Chip Mixed-Signal Test2010Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer.

    Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author.

    Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques.

    A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

    List of papers
    1. ADC on-Chip Dynamic Test by PWM Technique
    Open this publication in new window or tab >>ADC on-Chip Dynamic Test by PWM Technique
    2008 (English)In: International Conference on Signals and Electronic Systems, IEEE , 2008, 15-18 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-43029 (URN)10.1109/ICSES.2008.4673345 (DOI)70959 (Local ID)78-83-88309-47-2 (ISBN)70959 (Archive number)70959 (OAI)
    Conference
    International Conference on Signals and Electronic Systems, ICSES '08, 14-17 Sept, Krakow, Poland
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2010-11-17Bibliographically approved
    2. On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
    Open this publication in new window or tab >>On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
    2009 (English)In: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey, IEEE , 2009, 105-108 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.

    Place, publisher, year, edition, pages
    IEEE, 2009
    Keyword
    Stimuli generation, on-chip test
    National Category
    Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-20668 (URN)10.1109/ECCTD.2009.5274977 (DOI)000276473700027 ()978-1-4244-3896-9 (ISBN)
    Conference
    European Conference on Circuit Theory and Design, ECCTD 2009, 23-27 Aug., Antalya
    Note
    ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEEAvailable from: 2009-10-13 Created: 2009-09-16 Last updated: 2010-11-17Bibliographically approved
    3. Two-tone PLL for on-chip IP3 test
    Open this publication in new window or tab >>Two-tone PLL for on-chip IP3 test
    2010 (English)In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, 3549-3552 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

    Place, publisher, year, edition, pages
    IEEE, 2010
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-61666 (URN)10.1109/ISCAS.2010.5537812 (DOI)978-1-4244-5308-5 (ISBN)
    Conference
    Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
    4. Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
    Open this publication in new window or tab >>Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
    2010 (English)In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, 393-396 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

    Place, publisher, year, edition, pages
    IEEE, 2010
    National Category
    Signal Processing
    Identifiers
    urn:nbn:se:liu:diva-61668 (URN)978-1-4244-5307-8 (ISBN)
    Conference
    International Conference on Signals and Electronic Systems (ICSES), 7-10 Sept, Gliwice, Poland
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2015-09-14Bibliographically approved
    5. Design of Two-Tone RFGenerator for On-Chip IP3/IP2 Test
    Open this publication in new window or tab >>Design of Two-Tone RFGenerator for On-Chip IP3/IP2 Test
    (English)Manuscript (preprint) (Other academic)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-61669 (URN)
    Conference
    IEEE Transactions on Circuits and Systems–II
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
    6. One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
    Open this publication in new window or tab >>One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
    2010 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic) Submitted
    Place, publisher, year, edition, pages
    Springer, 2010
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-61687 (URN)
    Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2017-12-12Bibliographically approved
  • 3.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Two-tone PLL for on-chip IP3 test2010In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, 3549-3552 p.Conference paper (Refereed)
    Abstract [en]

    This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

  • 4.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Two-Tone PLL for on-Chip IP3 Test2010In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
  • 5.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ADC on-Chip Dynamic Test by PWM Technique2008In: International Conference on Signals and Electronic Systems, IEEE , 2008, 15-18 p.Conference paper (Refereed)
    Abstract [en]

    This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

  • 6.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator2010In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, 393-396 p.Conference paper (Refereed)
    Abstract [en]

    This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

  • 7.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of Two-Tone RFGenerator for On-Chip IP3/IP2 TestManuscript (preprint) (Other academic)
  • 8.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    On-Chip Spectral Test for High-Speed ADCs by ΣΔ Technique2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, 661-664 p.Conference paper (Refereed)
    Abstract [en]

    Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance spectral measurements a frequency plan is used taking into account the type of ΣΔ modulation (low-pass and band-pass) including the FFT processing gain. Higher order modulation schemes are avoided to manage the ΣΔ quantization noise without resorting to a more complicated filter. For spectral measurements up to the Nyquist frequency, we propose a dedicated low-pass/band-pass ΣΔ modulation scheme that limits spreading of the low-frequency quantization noise by ADC under test that tends to obstruct the test measurements at high frequencies. Correction technique for NRTZ encoding suitable for ADCs with very high clock frequencies is put in perspective. The presented technique is illustrated by simulation examples of a Nyquist-rate ADC under test.

  • 9.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique2009In: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey, IEEE , 2009, 105-108 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.

  • 10.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test2010In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic)
  • 11.
    Ahsan, Naveed
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reconfigurable and Broadband Circuits for Flexible RF Front Ends2009Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Most of today’s microwave circuits are designed for specific function and special need. There is a growing trend to have flexible and reconfigurable circuits. Circuits that can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured to achieve the desired performance seems to be challenging. However, with recent advances in many areas of technology these demands can now be met.

    Two concepts have been investigated in this thesis. The initial part presents the feasibility of a flexible and programmable circuit (PROMFA) that can be utilized for multifunctional systems operating at microwave frequencies. Design details and PROMFA implementation is presented. This concept is based on an array of generic cells, which consists of a matrix of analog building blocks that can be dynamically reconfigured. Either each matrix element can be programmed independently or several elements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters or oscillators. Realization of a flexible RF circuit based on generic cells is a new concept. In order to validate the idea, two test chips have been fabricated. The first chip implementation was carried out in a 0.2μm GaAs process, ED02AH from OMMICTM. The second chip was implemented in a standard 90nm CMOS process. Simulated and measured results are presented along with some key applications such as low noise amplifier, tunable band pass filter and a tunable oscillator.

    The later part of the thesis covers the design and implementation of broadband RF front-ends that can be utilized for multistandard terminals such as software defined radio (SDR). The concept of low gain, highly linear frontends has been presented. For proof of concept two test chips have been implemented in 90nm CMOS technology process. Simulated and measurement results are presented. These RF front-end implementations utilize wideband designs with active and passive mixer configurations.

    We have also investigated narrowband tunable LNAs. A dual band tunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuning technique has been proposed for the optimization of this LNA.

    List of papers
    1. Applications of Programmable Microwave Function Array (PROMFA)
    Open this publication in new window or tab >>Applications of Programmable Microwave Function Array (PROMFA)
    2007 (English)In: Proceedings of the IEEE European Conference on Circuit Theory and Design (ECCTD 2007), August 26-30, 2007, Seville, Spain, IEEE , 2007, 164 -167 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the use of programmable microwave function array (PROMFA) for different microwave application. The PROMFA concept is based on an array of generic cells, in which a number of different functions can be realized. Each PROMFA cell is a four-port circuit, that can either be programmed independently or collectively according to a specific need. Specifically, the phase shift capability in a single PROMFA cell, useful for a new type of phase shifter design is discussed. The paper also presents the functionality of this new architecture as a beamforming network. As an example case an active corporate feed network and a tunable recursive filter is demonstrated. Simulated and measured results are presented.

    Place, publisher, year, edition, pages
    IEEE, 2007
    Keyword
    Microwave circuits, phase shifters, programmable circuits, active corporate feed network, four-port circuit, generic cells, phase shift capability, programmable microwave function array, tunable recursive filter
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-14859 (URN)10.1109/ECCTD.2007.4529562 (DOI)978-1-4244-1341-6 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-01-13Bibliographically approved
    2. A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells
    Open this publication in new window or tab >>A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells
    Show others...
    2009 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic) Submitted
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

    Keyword
    CMOS, flexible circuit, generic PROMFA cells, reconfigurable circuit, tunable oscillator, tunable band pass filter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18508 (URN)
    Available from: 2009-05-29 Created: 2009-05-29 Last updated: 2017-12-13Bibliographically approved
    3. Dual Band Tunable LNA for Flexible RF Front End
    Open this publication in new window or tab >>Dual Band Tunable LNA for Flexible RF Front End
    2007 (English)In: Proceedings of the IEEE International Bhurban Conference on Applied Sciences & Technology (IBCAST 2007), January 8-11, 2007, Islamabad, Pakistan, IEEE Explore , 2007, 19-22 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

    Place, publisher, year, edition, pages
    IEEE Explore, 2007
    Keyword
    Circuit tuning, flexible electronics, gallium arsenide, low noise amplifiers, radiofrequency amplifiers, varactors, wireless LAN
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:liu:diva-14860 (URN)10.1109/IBCAST.2007.4379900 (DOI)978-969-8741-04-4 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-01-13Bibliographically approved
    4. A Self-Tuning Technique for Optimization of Dual Band LNA
    Open this publication in new window or tab >>A Self-Tuning Technique for Optimization of Dual Band LNA
    2008 (English)In: European Wireless Technology Conference (EuWiT), EuMW 2008, October 27-28, 2008, Amsterdam, The Netherlands, IEEE , 2008, 178-181 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a self-tuning technique for optimization of a dual band LNAthat can be used in a flexible RF front-end suitable for IEEE 802.11a/b/g WLANapplications. With this tuning technique the LNA can perform self-calibrationfor the optimal performance. A possible shift in resonance frequency due toprocess and temperature variations can be compensated by this method. Theproposed self-tuning technique is implemented by using a simple RF detector atthe LNA output. Based on the DC value provided by this detector the LNA istuned for a maximum gain through the tuning loop, which incorporates ADC,digital base-band and DAC. We show that the tuning error can be within halfLSB of ADC provided the DAC and ADC resolutions are constraint by aspecified condition. For 4-bit case this value corresponds to a gain error of0.4 dB. The LNA has been implemented in 0.2μm GaAs process offered byOMMICTM. In measurements the LNA achieves a gain of 15.1 dB and 21.6 dBin the upper and lower band, respectively, with corresponding NF of 3.8 dB and2.8 dB. In the lower band the measured IIP3 is -3 dBm and 1dB_CP is -8 dBm.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14862 (URN)978-2-87487-008-8 (ISBN)
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2009-05-29Bibliographically approved
    5. Highly Linear Wideband Low Power Current Mode LNA
    Open this publication in new window or tab >>Highly Linear Wideband Low Power Current Mode LNA
    2008 (English)In: Proceedings from the ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, IEEE , 2008, 73-76 p.Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents design considerations for low power, highly linear currentmode LNAs that can be used for wideband RF front-ends for multistandardapplications. The circuit level simulations of the proposed architecture indicatethat with optimal biasing a high value of IIP3 can be obtained. A comparison ofthree scenarios for optimal bias is presented. Simulation results indicate thatwith the proposed architecture, LNAs may achieve a maximum NF of 3.6 dBwith a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBmwith 6.3 mW power consumption. The LNAs have a broadband input match of 50Ω. The process is 90nm CMOS and with 1.1V supply the LNAs powerconsumption varies between 6.3 mW and 2.3 mW for the best and the worst caseIIP3, respectively.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14863 (URN)10.1109/ICSES.2008.4673361 (DOI)978-83-88309-47-2 (ISBN)978-83-88309-52-6 (ISBN)
    Conference
    International Conference on Signals and Electronic Systems (ICSES’08), September 14-17, 2008, Krakow, Poland
    Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2014-05-15Bibliographically approved
    6. A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
    Open this publication in new window or tab >>A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
    Show others...
    2009 (English)Manuscript (Other academic)
    Abstract [en]

    The software defined radio concept has emerged as a feasible solution for future multigand and multistandard receivers. The proposed software defined radio architecture needs a front-end with moderate or low gain, high linearity, and low noise figure. This paper presents the design and measurement results of low gain RF front-end in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transcjonductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match getter than -8dB up to 8GHz. The front-end achieves voltage conversion gain of 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz at 1GHz. The complete front-end consumers 23mW with active chip area of only 0.048mm2.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18196 (URN)
    Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2010-01-14Bibliographically approved
    7. A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
    Open this publication in new window or tab >>A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
    Show others...
    2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, 79-90 p.Article in journal (Refereed) Published
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

    Place, publisher, year, edition, pages
    SpringerLink, 2012
    Keyword
    Blocker suppression, common gate (CG), highly linear, low power, multi-standard, software defined radio, wideband front-end
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-18511 (URN)10.1007/s10470-011-9667-9 (DOI)000298604100007 ()
    Note
    The original status of this article was: Manuscript.Available from: 2009-05-29 Created: 2009-05-29 Last updated: 2017-12-13Bibliographically approved
  • 12.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Self-Tuning Technique for Optimization of Dual Band LNA2008In: European Wireless Technology Conference (EuWiT), EuMW 2008, October 27-28, 2008, Amsterdam, The Netherlands, IEEE , 2008, 178-181 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a self-tuning technique for optimization of a dual band LNAthat can be used in a flexible RF front-end suitable for IEEE 802.11a/b/g WLANapplications. With this tuning technique the LNA can perform self-calibrationfor the optimal performance. A possible shift in resonance frequency due toprocess and temperature variations can be compensated by this method. Theproposed self-tuning technique is implemented by using a simple RF detector atthe LNA output. Based on the DC value provided by this detector the LNA istuned for a maximum gain through the tuning loop, which incorporates ADC,digital base-band and DAC. We show that the tuning error can be within halfLSB of ADC provided the DAC and ADC resolutions are constraint by aspecified condition. For 4-bit case this value corresponds to a gain error of0.4 dB. The LNA has been implemented in 0.2μm GaAs process offered byOMMICTM. In measurements the LNA achieves a gain of 15.1 dB and 21.6 dBin the upper and lower band, respectively, with corresponding NF of 3.8 dB and2.8 dB. In the lower band the measured IIP3 is -3 dBm and 1dB_CP is -8 dBm.

  • 13.
    Ahsan, Naveed
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ouacha, Aziz
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A tunable LNA for flexible RF front-end.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 14.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dual Band Tunable LNA for Flexible RF Front End2007In: Proceedings of the IEEE International Bhurban Conference on Applied Sciences & Technology (IBCAST 2007), January 8-11, 2007, Islamabad, Pakistan, IEEE Explore , 2007, 19-22 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

  • 15.
    Ahsan, Naveed
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ouacha, Aziz
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Samuelsson, Carl
    FOI, Linköping.
    Boman, Tomas
    FOI, Linköping.
    A widely tunable filter using generic PROMFA cells.2007In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper (Refereed)
  • 16.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Boman, Tomas
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Applications of Programmable Microwave Function Array (PROMFA)2007In: Proceedings of the IEEE European Conference on Circuit Theory and Design (ECCTD 2007), August 26-30, 2007, Seville, Spain, IEEE , 2007, 164 -167 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the use of programmable microwave function array (PROMFA) for different microwave application. The PROMFA concept is based on an array of generic cells, in which a number of different functions can be realized. Each PROMFA cell is a four-port circuit, that can either be programmed independently or collectively according to a specific need. Specifically, the phase shift capability in a single PROMFA cell, useful for a new type of phase shifter design is discussed. The paper also presents the functionality of this new architecture as a beamforming network. As an example case an active corporate feed network and a tunable recursive filter is demonstrated. Simulated and measured results are presented.

  • 17.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic)
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

  • 18.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Highly Linear Wideband Low Power Current Mode LNA2008In: Proceedings from the ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, IEEE , 2008, 73-76 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents design considerations for low power, highly linear currentmode LNAs that can be used for wideband RF front-ends for multistandardapplications. The circuit level simulations of the proposed architecture indicatethat with optimal biasing a high value of IIP3 can be obtained. A comparison ofthree scenarios for optimal bias is presented. Simulation results indicate thatwith the proposed architecture, LNAs may achieve a maximum NF of 3.6 dBwith a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBmwith 6.3 mW power consumption. The LNAs have a broadband input match of 50Ω. The process is 90nm CMOS and with 1.1V supply the LNAs powerconsumption varies between 6.3 mW and 2.3 mW for the best and the worst caseIIP3, respectively.

  • 19.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, 79-90 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

  • 20.
    Al-Taie, Mahir Jabbar Rashid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Comparison of EDMOS and Cascode Structures for PA Design in 65 nm CMOS Technology2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link.

    The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity.

    The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

  • 21.
    Alvandporu, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Impact of Miller Capacitance on Power Consumption1998In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1998, 83-92 p.Conference paper (Refereed)
  • 22.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Domino circuit2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage lin

  • 23.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Enhanced domino circuit2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

  • 24.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-Performance and Low-Power Challenges for Sub-70nm System on Chip. Invited talk2003In: International workshop on Circuit Design (IWCD 2004), June 17, National Taiwan University, Taipei, Taiwan, 2003Conference paper (Other academic)
  • 25.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-performance and Low-voltage Datapath and Interconnect Design Challenges2004In: In proceedings of: 12th IEEE Mediterranean Electrotechnical Conference, MELECON, 12-15 May, Dubrovnik, Croatia, 2004Conference paper (Refereed)
  • 26.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arakawa, Fumio
    Hitachi, Tokyo, Japan.
    Session 20 overview - processor building blocks2005Conference paper (Other (popular science, discussion, etc.))
  • 27.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arimoto, Kazutami
    Renesas Corp, Itami, Hyogo 6640005 Japan .
    Cantatore, Eugenio
    Eindhoven University Technology, NL-5600 MB Eindhoven, Netherlands .
    Zhang, Kevin
    Intel Corp, Hillsboro, OR 97124 USA .
    Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 1, 3-6 p.Article in journal (Other academic)
    Abstract [en]

    n/a

  • 28.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Balamurugan, G.
    Intel Corp., USA.
    Soumyanath, K.
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Leakage-tolerant circuit and method for large register files2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.

  • 29.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Multi-phase clock generation and synchronization2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A method for controlling a local clock includes receiving a reference clock and generating a phase-shifted version of the reference clock. The two clocks are synchronized using a closed-loop method that produces a control signal. The control signal is smoothed during the closed-loop method and the smoothed signal is then used, instead of the control signal, in generating the phase-shifted clock

  • 30.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Intel Corporation, Hillsboro, USA.
    Borkar, S.
    Intel Corporation, Hillsboro, USA.
    Rahman, A.
    Intel Corporation, Hillsboro, USA.
    Webb, C.
    Intel Corporation, Hillsboro, USA.
    A burn-in tolerant dynamic circuit technique2002In: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, 81-84 p.Conference paper (Refereed)
  • 31.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Conditional Keeper Technique for Sub-0.13mm Wide Dynamic Gates2001In: In proceedings of: International Symposium on VLSI Circuits, 2001, 29-30 p.Conference paper (Refereed)
  • 32.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Sournyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Low-Leakage Dynamic Multi-Ported Register file in 0.13mm CMOS2001In: ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design, New York, USA: ACM , 2001, 68-71 p.Conference paper (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256X32b 4-read/write-port Register-File for ~6GHz operation at 1.2V in a 0.13 utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned remains are able to improve upon all-low-Vt performance by 4%, while maintaining Dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5X.

     

  • 33.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Conditional burn-in keeper for dynamic circuits2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

  • 34.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Fast static receiver with input dependent inversion threshold.2006Patent (Other (popular science, discussion, etc.))
  • 35.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Voltage-level converter2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.

  • 36.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram K.
    Intel Corp., Hillsboro, USA.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Apperson, Stuart
    Intel Corp., Hillsboro, USA.
    Bloechel, Bradley
    Intel Corp., Hillsboro, USA.
    Borkar, Shekar
    Intel Corp., Hillsboro, USA.
    A 3.5GHz 32mW 150nm multiphase clock generator for high-performande microprocessors.2003In: IEEE International Solid-State Circuits Conference.,2003, Augusta, Maine: J.S.McCarthy Printers , 2003, 112- p.Conference paper (Refereed)
  • 37.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 38.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corsp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 39.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 40.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Inten Corp., USA.
    Narendra, Siva
    Inten Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 41.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 42.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A sub-130-nm conditional keeper technique2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, 633-638 p.Article in journal (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

  • 43.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp, USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Fast dual-rail dynamic logic style2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 44.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Flash (II)-Domino: a fast dual-rail dynamic logic style2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 45.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits1999In: In proceedings of: IEEE International Conference on Electronics, Circuits, And System, 1999, 209-212 p.Conference paper (Refereed)
    Abstract [en]

     

  • 46.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering2000In: In proceedings of: IEEE International Symposium on Circuits and Systems. Vol.5, IEEE , 2000, 465-468 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, interconnection length estimation is discussed and a general, simple, fast and efficient estimation technique is proposed. In contrast to traditional average length estimation techniques, such as the one based on Rent's rule, the new technique utilizes the topological information of the actual netlist and estimates the length of each interconnection separately. The result of the estimation can be directly used to assign a reasonable R and C to each interconnect, including long and wide buses. Consequently, the new technique enhances the accuracy of power and delay estimations at higher design levels of abstraction

  • 47.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits1998In: ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design, 1998, 245-249 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a Vdd close to VT and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low Vdd. To avoid reducing Vdd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to VT based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

  • 48.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Manoj, Sinha
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Differential charge transfer sense ampliifier2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.

  • 49.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mathew, S.
    Intel Corp., USA.
    Advanced high-performance microprocessor design challenges and solutions2002In: Proceedings of 15th Annual IEEE International ASIC/SOC Conference, 2002, 476-476 p.Conference paper (Refereed)
  • 50.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reynaert, Patrick
    Katholieke University of Leuven, Belgium .
    Ytterdal, Trond
    Norwegian University of Science and Technology, Norway .
    Editorial Material: Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC)2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, 1511-1514 p.Article in journal (Other academic)
    Abstract [en]

    n/a

1234567 1 - 50 of 510
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf