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  • 1.
    Alvandporu, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Impact of Miller Capacitance on Power Consumption1998In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1998, 83-92 p.Conference paper (Refereed)
  • 2.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Domino circuit2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage lin

  • 3.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Enhanced domino circuit2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

  • 4.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-Performance and Low-Power Challenges for Sub-70nm System on Chip. Invited talk2003In: International workshop on Circuit Design (IWCD 2004), June 17, National Taiwan University, Taipei, Taiwan, 2003Conference paper (Other academic)
  • 5.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-performance and Low-voltage Datapath and Interconnect Design Challenges2004In: In proceedings of: 12th IEEE Mediterranean Electrotechnical Conference, MELECON, 12-15 May, Dubrovnik, Croatia, 2004Conference paper (Refereed)
  • 6.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arakawa, Fumio
    Hitachi, Tokyo, Japan.
    Session 20 overview - processor building blocks2005Conference paper (Other (popular science, discussion, etc.))
  • 7.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arimoto, Kazutami
    Renesas Corp, Itami, Hyogo 6640005 Japan .
    Cantatore, Eugenio
    Eindhoven University Technology, NL-5600 MB Eindhoven, Netherlands .
    Zhang, Kevin
    Intel Corp, Hillsboro, OR 97124 USA .
    Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 1, 3-6 p.Article in journal (Other academic)
    Abstract [en]

    n/a

  • 8.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Balamurugan, G.
    Intel Corp., USA.
    Soumyanath, K.
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Leakage-tolerant circuit and method for large register files2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.

  • 9.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Multi-phase clock generation and synchronization2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A method for controlling a local clock includes receiving a reference clock and generating a phase-shifted version of the reference clock. The two clocks are synchronized using a closed-loop method that produces a control signal. The control signal is smoothed during the closed-loop method and the smoothed signal is then used, instead of the control signal, in generating the phase-shifted clock

  • 10.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Intel Corporation, Hillsboro, USA.
    Borkar, S.
    Intel Corporation, Hillsboro, USA.
    Rahman, A.
    Intel Corporation, Hillsboro, USA.
    Webb, C.
    Intel Corporation, Hillsboro, USA.
    A burn-in tolerant dynamic circuit technique2002In: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, 81-84 p.Conference paper (Refereed)
  • 11.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Conditional Keeper Technique for Sub-0.13mm Wide Dynamic Gates2001In: In proceedings of: International Symposium on VLSI Circuits, 2001, 29-30 p.Conference paper (Refereed)
  • 12.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Sournyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Low-Leakage Dynamic Multi-Ported Register file in 0.13mm CMOS2001In: ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design, New York, USA: ACM , 2001, 68-71 p.Conference paper (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256X32b 4-read/write-port Register-File for ~6GHz operation at 1.2V in a 0.13 utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned remains are able to improve upon all-low-Vt performance by 4%, while maintaining Dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5X.

     

  • 13.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Conditional burn-in keeper for dynamic circuits2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

  • 14.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Fast static receiver with input dependent inversion threshold.2006Patent (Other (popular science, discussion, etc.))
  • 15.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Voltage-level converter2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.

  • 16.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram K.
    Intel Corp., Hillsboro, USA.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Apperson, Stuart
    Intel Corp., Hillsboro, USA.
    Bloechel, Bradley
    Intel Corp., Hillsboro, USA.
    Borkar, Shekar
    Intel Corp., Hillsboro, USA.
    A 3.5GHz 32mW 150nm multiphase clock generator for high-performande microprocessors.2003In: IEEE International Solid-State Circuits Conference.,2003, Augusta, Maine: J.S.McCarthy Printers , 2003, 112- p.Conference paper (Refereed)
  • 17.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 18.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corsp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 19.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 20.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Inten Corp., USA.
    Narendra, Siva
    Inten Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 21.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 22.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A sub-130-nm conditional keeper technique2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, 633-638 p.Article in journal (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

  • 23.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp, USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Fast dual-rail dynamic logic style2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 24.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Flash (II)-Domino: a fast dual-rail dynamic logic style2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 25.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits1999In: In proceedings of: IEEE International Conference on Electronics, Circuits, And System, 1999, 209-212 p.Conference paper (Refereed)
    Abstract [en]

     

  • 26.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering2000In: In proceedings of: IEEE International Symposium on Circuits and Systems. Vol.5, IEEE , 2000, 465-468 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, interconnection length estimation is discussed and a general, simple, fast and efficient estimation technique is proposed. In contrast to traditional average length estimation techniques, such as the one based on Rent's rule, the new technique utilizes the topological information of the actual netlist and estimates the length of each interconnection separately. The result of the estimation can be directly used to assign a reasonable R and C to each interconnect, including long and wide buses. Consequently, the new technique enhances the accuracy of power and delay estimations at higher design levels of abstraction

  • 27.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits1998In: ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design, 1998, 245-249 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a Vdd close to VT and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low Vdd. To avoid reducing Vdd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to VT based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

  • 28.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Manoj, Sinha
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Differential charge transfer sense ampliifier2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.

  • 29.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mathew, S.
    Intel Corp., USA.
    Advanced high-performance microprocessor design challenges and solutions2002In: Proceedings of 15th Annual IEEE International ASIC/SOC Conference, 2002, 476-476 p.Conference paper (Refereed)
  • 30.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reynaert, Patrick
    Katholieke University of Leuven, Belgium .
    Ytterdal, Trond
    Norwegian University of Science and Technology, Norway .
    Editorial Material: Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC)2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, 1511-1514 p.Article in journal (Other academic)
    Abstract [en]

    n/a

  • 31.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Somasekhar, D.
    Intel Corp., USA.
    Hsu, S.
    Intel Corp., USA.
    Krishnamurthy, R.
    Intel Corp., USA.
    De, V.
    Intel Corp., USA.
    Statis random access memory with symmetric leakage-compensated bit line.2004Patent (Other (popular science, discussion, etc.))
  • 32.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Somasekhar, D.
    Intel Corp., Hillsboro, USA.
    Krishnamurthy, Ram
    Intel Corp., Hillsboro, USA.
    De, V.
    Intel Corp., Hillsboro, USA.
    Borkar, S.
    Intel Corp., Hillsboro, USA.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Bitline leakage equalization for sub-100nm caches.2003In: ESSCIRC 2003,2003, Lissabon: Grafica Maiadouro SA , 2003, 401- p.Conference paper (Refereed)
  • 33.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Soumyanath, K.
    Intel Corp., USA.
    Krishnamurthy, R.
    Intel Corp., USA.
    Integrated circuits bus architecture including a full-swing, clocked, commongate receiver for fast on-chip signal transmission.2002Patent (Other (popular science, discussion, etc.))
  • 34.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Soumynath, K.
    Intel Corp., USA.
    Krishnamurthy, R.
    Intel Corp., USA.
    Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates.2003Patent (Other (popular science, discussion, etc.))
  • 35.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction1997In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1997, 305-314 p.Conference paper (Refereed)
    Abstract [en]

    A new wire estimation technique is presented. It utilizes the topology of the netlist and is sensitive to the actual design. It has the unique quality to estimate the length of every power consuming interconnection individually. Compared to other wire length estimation techniques which use average or total wire length, the result of the new technique shows a strong correlation with the result of "real" automatic placement and route tools. Hence it can estimate a reasonable wire capacitance for each interconnection. The individual wire lengths, combined with individual node activities, are essential for an accurate power estimation.

  • 36.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Improving Cell Libraries for Low Power Design1996In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1996, 317-325 p.Conference paper (Refereed)
  • 37.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Caputa, Peter
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Hansson, Martin
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    TSEK 01, VLSI design projekt 20042003Other (Other (popular science, discussion, etc.))
  • 38.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Carlsson, Ingvar
    EK-ISY Linköpings universitet.
    Natarajan, Sreedhar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 128Kb 5T SRAM in 0.18mm CMOS.2007In: International Conference on Memory Technology and Design ICMTD 2007,2007, 2007, 185- p.Conference paper (Refereed)
  • 39.
    Azam, Sher
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Jonsson, Rolf
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    High Power, Single Stage SiGaN HEMT Class E Power Amplifier at GHz Frequencies2010In: IEEE International Bhurban Conference on Applied Sciences and Technology, IEEE , 2010Conference paper (Refereed)
  • 40.
    Azam, Sher
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Jonsson, Rolf
    Swedish Defense Research Agency (FOI), Box 1165, SE-581 11 Linkoping, Sweden.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    High Power, Single Stage SiGaN HEMT Class EPower Amplifier at GHz FrequenciesManuscript (preprint) (Other academic)
    Abstract [en]

    A high power single stage class E power amplifier is implemented with lumped elements at 0.89-1.02GHz using Silicon GaN High Electron Mobility Transistor as an active device. The maximum drain efficiency (DE) and power added efficiency (PAE) of 67 and 65 % respectively is obtained with a maximum output power of 42.2 dBm (~ 17 W) and amaximum power gain of 15 dB. We obtained good results at all measured frequencies.

  • 41.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, 2306-2310 p.Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

  • 42.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators2013In: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

  • 43.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Timing challenges in high-speed interleaved ΔΣ DACs2014In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, 46-49 p.Conference paper (Refereed)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

  • 44.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmailzadeh Najari, Omid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS2013In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, 387-391 p.Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

  • 45.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ojani, Amin
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, 646-650 p.Article in journal (Refereed)
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

  • 46.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-Speed On-Chip Interconnect Modeling for Circuit Simulation2004In: Proceedings of the Norchip Conference, Oslo, Norway, November, 2004, 143-146 p.Conference paper (Other academic)
  • 47.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An extended transition energy cost model for buses in deep submicron technologies2004In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings / [ed] Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou, Springer Berlin/Heidelberg, 2004, Vol. 3254, 849-858 p.Chapter in book (Refereed)
    Abstract [en]

    In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

  • 48.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies2004In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece, 2004, 849-858 p.Conference paper (Other academic)
  • 49.
    Carlsson, Ingvar
    et al.
    EK. ISY, LiU.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Natarajan, S
    MoSys.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A high density, low leakage, 5T SRAM for embedded caches2004In: ESSCIRC 2004,2004, Leuven: IEEE, Inc. , 2004, 215- p.Conference paper (Refereed)
  • 50.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, 43-53 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

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