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  • 1.
    Di, Wu
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nilsson, Anders
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Coresonic AB, Linköping.
    Alfredsson, Erik
    Coresonic AB, Linköping.
    System Architecture for 3GPP LTE Modem Using a Programmable Baseband Processo2009In: International Symposium on System-on-Chip (SoC 2009), 2009Conference paper (Refereed)
    Abstract [en]

    3G evolution towards HSPA and LTE is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.

  • 2. Jiao, Haiyan
    et al.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Tell, Eric
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    MIPS Cost Estimation for OFDM-VBLAST systems2006In: WCNC, IEEE Wireless Communications and Networking,2006, 2006Conference paper (Refereed)
  • 3.
    Liu, Dake
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nilsson, Anders
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Bridging Dream and Reality: Programmable Baseband Processors for Software-Defined Radio2009In: IEEE COMMUNICATIONS MAGAZINE, ISSN 0163-6804, Vol. 47, no 9, p. 134-140Article in journal (Refereed)
    Abstract [en]

    A programmable radio baseband signal processor is one of the essential enablers of software-defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.

  • 4.
    Liu, Dake
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Tell, Eric
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Implemenation of Programmable Baseband Processors2004In: CCIC,2004, 2004Conference paper (Refereed)
  • 5.
    Liu, Dake
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Tell, Eric
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Söderquist, Ingemar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Fully flexible baseband DSP processors for future SDR/JTRS2005In: Western European Armaments Organization WEAO,2005, 2005Conference paper (Other academic)
  • 6.
    Nilsson, Anders
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Design of multi-standard baseband processors2005Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. The ever changing wireless network industry also requires flexible and versatile baseband processors to be able to adapt quickly to new and updated standards. The convergence of mobile communication devices and systems require multi-standard capabilities in the processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM, CDMA and single carrier modulation with the same processing device. All this requires a programmable baseband processor because a pure fixed-function ASIC solution is not flexible enough. Furthermore, ASIC solutions for multi-standard baseband processing are less area efficient than their programmable counterparts since processing resources cannot efficiently be shared between different operations and standards. This project was initiated for the above mentioned reason as a continuation of a previous baseband processor project at the research group. Accordingly, this thesis is devoted to the design of area efficient, low clock rate, fully programmable baseband processors. A reduction of the clock rate will simplify the design of the processor as well as save power in the application. Since most multi-standard processing devices will be used in a mobile environment, low power is essential. Normally, extra computing resources must be added to a system designed for low clock rate operation compared to a regular solution, resulting in a higher area and complexity of the chip. In this project effort has been made to create efficient base architectures maintaining a low area and clock rate while also maintaining flexibility and processing capability. At the same time design methods for the required DSP execution units within the processor have been developed.

    Usually general baseband processing includes many tasks such as error control coding/ decoding, interleaving, scrambling etc, however in this thesis because of time and resource limitations, the focus is on the symbol related processing, although the bit manipulation and forward error correction tasks are also studied regarding acceleration.

    List of papers
    1. An accelerator structure for programmable multi-standard baseband processors
    Open this publication in new window or tab >>An accelerator structure for programmable multi-standard baseband processors
    2004 (English)In: Proceedings of the Intl. conference on Wireless networks and Emerging technologies, WNET2004 / [ed] A.O. Fapojuwo, 2004, p. 644-649Conference paper, Published paper (Other academic)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14525 (URN)0-88986-403-9 (ISBN)
    Conference
    Wireless Networks and Emerging Technologies(WNET 2004) July 8 – 10, 2004. Banff, Canada.
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2013-11-06
    2. A fully programmable Rake-receiver architecture for multi-standard baseband processors
    Open this publication in new window or tab >>A fully programmable Rake-receiver architecture for multi-standard baseband processors
    2005 (English)In: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, p. 292-297Conference paper, Published paper (Other academic)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

    Keywords
    CDMA, Rake, MRC, DSP, SDR
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14524 (URN)
    Conference
    The Intl. conference on Networks and Communication systems, NCS2005. Krabi, Thailand 2005.
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2013-11-06
    3. Design methodology for memory-efficient multi-standard baseband processors
    Open this publication in new window or tab >>Design methodology for memory-efficient multi-standard baseband processors
    2005 (English)In: Asia Pacific Communication Conference, Perth, Australia, 2005, p. 28-32Conference paper, Published paper (Other academic)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14522 (URN)10.1109/APCC.2005.1554012 (DOI)0-7803-9132-2 (ISBN)
    Conference
    2005 Asia-Pacific Conference on Communications (APCC). 3-5 October, 2005. Perth, Australia.
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2013-11-06
  • 7.
    Nilsson, Anders
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Design of programmable multi-standard baseband processors2007Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. Programmability can also be used to quickly adapt to new and updated standards within the ever changing wireless communication industry since a pure ASIC solution will not be flexible enough. ASIC solutions for multi-standard baseband processing are also less area efficient than their programmable counterparts since processing resources cannot be efficiently shared between different operations. However, as baseband processing is computationally demanding, traditional DSP architectures cannot be used due to their limited computing capacity. Instead VLIW- and SIMD-based processors are used to provide sufficient computing capacity for baseband applications. The drawback of VLIW-based DSPs is their low power efficiency due to the wide instructions that need to be fetched every clock cycle and their control-path overhead. On the other hand, pure SIMD-based DSPs lack the possibility to perform different concurrent operations. Since memory access power is the dominating part of the power consumption in a processor, other alternatives should be investigated.

    In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named ``Single Instruction stream Multiple Tasks'', SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor. The contributions of this project are the design and research of key architectural components in the SIMT architecture as well as development of design methodologies. Methodologies for accelerator selection are also presented. Furthermore data dependency control and memory management are studied. Architecture and performance characteristics have also been compared between the SIMT and more traditional processor architectures.

    A complete system is demonstrated by the BBP2 baseband processor that has been designed using SIMT technology. The SIMT principle has previously been proven in a small scale in silicon in the BBP1 processor implementing a Wireless LAN transceiver. The second demonstrator chip (BBP2) was manufactured early 2007 and implements a full scale system with multiple SIMD clusters and a controller core supporting multiple threads. It includes enough memory to run symbol processing of DVB-H/T, WiMAX, IEEE 802.11a/b/g and WCDMA, and the silicon area is 11 mm2 in a 0.12 um CMOS technology.

  • 8.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Area efficient fully programmable baseband processors2007In: SAMOSVII Workshop; SAMOS, Greece, July 16-19, 2007Conference paper (Refereed)
  • 9.
    Nilsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Multi-standard support in SIMT programmable baseband processors2006In: SSoCC Swedish System-on-chip Conference,2006, 2006Conference paper (Other academic)
  • 10.
    Nilsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Processor friendly peak-to-average reduction in multi-carrier systems2004In: Swedish system-on-Chip Conference, SSoCC 04,2004, 2004Conference paper (Other academic)
  • 11.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    A fully programmable Rake-receiver architecture for multi-standard baseband processors2005In: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, p. 292-297Conference paper (Other academic)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

  • 12.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    A Programmable SIMD-based Multi-standard Rake Receiver Architecture2005In: European Signal Processing Conference, EUSIPCO, Antalya, Turkey, 2005Conference paper (Other academic)
    Abstract [en]

    Programmability with its associated flexibility will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and MRC-based channel equalization for several CDMA-based wireless transmission systems in software. Our processor is based on a DSP core with SIMD-computing clusters. We have mapped Rake receiver kernel-functions supporting several 3G standards to this micro-architecture and benchmarking shows that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA FDD/TDD-modes and HSDPA at clock rate not exceeding 76 MHz during soft handover conditions.

  • 13.
    Nilsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Tell, Eric
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Acceleration in multi-standard baseband processors2005In: Radiovetenskap och Kommunikation,2005, 2005Conference paper (Refereed)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an architecture for fully programmable baseband processing, based on a programmable DSP processor and a number of configurable accelerators which communicate via a configurable network. Acceleration of common cycleconsuming DSP jobs is necessary in order to manage wide-band modulation schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband processor supporting a number of common Wireless LAN and 3G standards. Benchmarking show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

  • 14.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    An 11 mm(2), 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12 mu m CMOS2009In: IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA: Vol 44, number 1, IEEE , 2009, Vol. 44, no 1, p. 90-97Conference paper (Refereed)
    Abstract [en]

    With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm(2) in a 0.12 mu m CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.

  • 15.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    An accelerator structure for programmable multi-standard baseband processors2004In: Proceedings of the Intl. conference on Wireless networks and Emerging technologies, WNET2004 / [ed] A.O. Fapojuwo, 2004, p. 644-649Conference paper (Other academic)
    Abstract [en]

    Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.

  • 16.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Simultaneous multistandard support in programmable baseband processors2006In: Proceedings of IEEE PRIME 2006, Otranto, Italy, 2006Conference paper (Refereed)
  • 17.
    Nilsson, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wiklund, Daniel
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Design methodology for memory-efficient multi-standard baseband processors2005In: Asia Pacific Communication Conference, Perth, Australia, 2005, p. 28-32Conference paper (Other academic)
    Abstract [en]

    Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory.

  • 18.
    Tell, Eric
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Low Area and Low Power Programmable Baseband Processor Architecture2005In: International workshop on SoC for real-time applications,2005, 2005Conference paper (Refereed)
  • 19.
    Tell, Eric
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Programmable DSP core for Baseband Processing2005In: IEEE Northeast Workshop on Circuits and Systems NEWCAS,2005, 2005Conference paper (Refereed)
  • 20.
    Tell, Eric
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Nilsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Implementation of a Programmable Baseband Processor2005In: Radiovetenskap och Kommunikation RVK,2005, 2005Conference paper (Refereed)
1 - 20 of 20
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