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  • 1.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Area Efficient Floating-Point Adder and Multiplier with IEEE-754 Compatible Semantics2014Conference paper (Refereed)
    Abstract [en]

    In this paper we describe an open source floating-point adder andmultiplier implemented using a 36-bit custom number format based onradix-16 and optimized for the 7-series FPGAs from Xilinx. Althoughthis number format is not identical to the single-precision IEEE-754format, the floating-point operators are designed in such a way thatthe numerical results for a given operation will be identical to theresult from an IEEE-754 compliant operator with support forround-to-nearest even, NaNs and Infs, and subnormalnumbers. The drawback of this number format is that the rounding stepis more involved than in a regular, radix-2 based operator. On theother hand, the use of a high radix means that the area costassociated with normalization and denormalization can be reduced,leading to a net area advantage for the custom number format, underthe assumption that support for subnormal numbers is required.

    The area of the floating-point adder in a Kintex-7 FPGA is 261 sliceLUTs and the area of the floating-point multiplier is 235 slice LUTsand 2 DSP48E blocks. The adder can operate at 319 MHz and themultiplier can operate at a frequency of 305 MHz.

  • 2.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Aspects of system-on-chip design for FPGAs2008Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Due to the increasing NRE costs of recent ASICs, the use of FPGAs is expected to continue to increase. While the first FPGAs were limited devices useful mainly for glue logic, todays FPGAs are highly capable devices used in many different application areas including telecommunication, multimedia, medical, and automotive. This means that many VLSI designers need to deal with FPGAs, either as the primary target, or as a prototype platform. The design methodology for an ASIC and FPGA are similar, but if high performance is expected from the FPGA, it is necessary to take FPGA limitations related to memories, data path components, I/O, and routing delays into account early in the design cycle for both FPGA prototyping and FPGA products.

    This thesis investigates these limitations through three case studies of important VLSI building blocks. The thesis also discusses how a designer can gain additional information from the FPGA backend flow through custom tools and presents a framework for designing such tools.

    The first case study discusses the opportunities and problems when designing both the data path and control path components of a high speed processor in an FPGA. The resulting processor core is a RISC processor with some DSP extensions which has a clock frequency which is significantly higher than the Micro blaze processor which has been specifically developed for Xilinx FPGAs. This case study focuses on the tradeoffs which are necessary to reach this performance in an FPGA.

    The second case study describes how a floating point adder and multiplier can be optimized for FPGAs. This is a very important area as the use of floating point arithmetic can significantly reduce the design time of some applications. The solution presented in the thesis outperforms previous academic publications and has a performance similar to commercial offerings.

    The third case study presents a packet switched Network-on-Chip (NoC) architecture. While NoCs are not commonly used in FPGA designs today it is expected that they will become an important component in future FPGA designs, especially when prototyping large NoC based ASICs.

    Finally, a framework is presented which allows a designer to write custom backend tool by modifying Xilinx XDL files. While the framework is already useful for some tasks, the main reason for including it is to inspire both researchers and developers to look into this area by showing that it is actually quite easy to write such tools.

    List of papers
    1. High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
    Open this publication in new window or tab >>High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
    2006 (English)In: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, p. 31-34Conference paper, Published paper (Refereed)
    Abstract [en]

    Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-100922 (URN)10.1109/NORCHP.2006.329238 (DOI)9781424407729 (ISBN)
    Conference
    24th Norchip Conference, 20-21 November 2006, Linkoping, Sweden.
    Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2015-02-18
    2. An FPGA based Open Source Network-on-chip Architecture
    Open this publication in new window or tab >>An FPGA based Open Source Network-on-chip Architecture
    2007 (English)In: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, IEEE , 2007, p. 800-803Conference paper, Published paper (Refereed)
    Abstract [en]

    Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

    Place, publisher, year, edition, pages
    IEEE, 2007
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16560 (URN)10.1109/FPL.2007.4380772 (DOI)978-1-4244-1060-6 (ISBN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    3. Thinking outside the flow: Creating customized backend tools for Xilinx based designs
    Open this publication in new window or tab >>Thinking outside the flow: Creating customized backend tools for Xilinx based designs
    2007 (English)In: 4th annual FPGAworld Conference, Stockholm, 2007, 2007Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper is intended to serve as an introduction to how to build a customized backend tool for a Xilinx based design flow. A Python based library called PyXDL is presented which allows a user to manipulate XDL files which contain a placed and routed design. Three different tools are presented which uses this library, ranging from a simple resource utilization viewer to a tool which will insert a logic analyzer into an already routed design, thus avoiding a costly complete rerun of the place and route tool.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16561 (URN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    4. A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
    Open this publication in new window or tab >>A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
    2008 (English)In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008, p. 599-602Conference paper, Published paper (Refereed)
    Abstract [en]

    As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16562 (URN)10.1109/FPL.2008.4630018 (DOI)978-1-4244-1960-9 (ISBN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
  • 3.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    EBRAM - Extending the BlockRAMs in FPGAs to support caches and hash tables inan efficient manner2012Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss how a typical Block RAM in an FPGA can be extended to enable the implementation of more efficient caches in FPGAs with very minor modifications to the existing Block RAM architectures. In addition, the modifications also allow other components, such as hash tables, to be implemented more efficiently.

  • 4.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Optimizing Xilinx designs through primitive instantiation2010In: FPGAworld '10 Proceedings of the 7th FPGAworld Conference, New York: ACM , 2010, p. 20-27Conference paper (Refereed)
    Abstract [en]

    This paper is intended as a guideline for people who are interested in manual instantiation of FPGA primitives as a way of improving the performance of an FPGA design. The focus of the paper is on designs where slice primitives like flip-fops and lookup tables are instantiated. Guidelines on how to develop a design with manual instantiation are presented together with a case study of a high performance bitserial two's complement divider where a majority of the area is manually instantiated. This divider is capable of reaching a maximum frequency of 345 MHz in the fastest Virtex-4 while utilizing less than 150 LUTs thanks to the high amount of manual optimizations. An open source library containing modules intended to promote the structured development of modules with manually instantiated components is also presented.

  • 5.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Performance driven FPGA design with an ASIC perspective2009Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient.

    This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA.

    Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA.

    The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated.

    All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs.

    Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

    List of papers
    1. Using low precision floating point numbers to reduce memory cost for MP3 decoding
    Open this publication in new window or tab >>Using low precision floating point numbers to reduce memory cost for MP3 decoding
    2004 (English)In: International Workshop on Multimedia Signal Processing, IEEE Xplore , 2004, p. 119-122Conference paper, Published paper (Refereed)
    Abstract [en]

    The purpose of our work has been to evaluate the practicality of using a 16-bit floating point representation to store the intermediate sample values and other data in memory during the decoding of MP3 bit streams. A floating point number representation offers a better trade-off between dynamic range and precision than a fixed point representation for a given word length. Using a floating point representation means that smaller memories can be used which leads to smaller chip area and lower power consumption without reducing sound quality. We have designed and implemented a DSP processor based on 16-bit floating point intermediate storage. The DSP processor is capable of decoding all MP3 bit streams at 20 MHz and this has been demonstrated on an FPGA prototype.

    Place, publisher, year, edition, pages
    IEEE Xplore, 2004
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16559 (URN)10.1109/MMSP.2004.1436435 (DOI)0-7803-8578-0 (ISBN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    2. An FPGA based Open Source Network-on-chip Architecture
    Open this publication in new window or tab >>An FPGA based Open Source Network-on-chip Architecture
    2007 (English)In: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, IEEE , 2007, p. 800-803Conference paper, Published paper (Refereed)
    Abstract [en]

    Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

    Place, publisher, year, edition, pages
    IEEE, 2007
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16560 (URN)10.1109/FPL.2007.4380772 (DOI)978-1-4244-1060-6 (ISBN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    3. Thinking outside the flow: Creating customized backend tools for Xilinx based designs
    Open this publication in new window or tab >>Thinking outside the flow: Creating customized backend tools for Xilinx based designs
    2007 (English)In: 4th annual FPGAworld Conference, Stockholm, 2007, 2007Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper is intended to serve as an introduction to how to build a customized backend tool for a Xilinx based design flow. A Python based library called PyXDL is presented which allows a user to manipulate XDL files which contain a placed and routed design. Three different tools are presented which uses this library, ranging from a simple resource utilization viewer to a tool which will insert a logic analyzer into an already routed design, thus avoiding a costly complete rerun of the place and route tool.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16561 (URN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    4. A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
    Open this publication in new window or tab >>A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
    2008 (English)In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008, p. 599-602Conference paper, Published paper (Refereed)
    Abstract [en]

    As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16562 (URN)10.1109/FPL.2008.4630018 (DOI)978-1-4244-1960-9 (ISBN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    5. High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
    Open this publication in new window or tab >>High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
    2008 (English)In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, p. 305-313Article in journal (Refereed) Published
    Abstract [en]

    There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16563 (URN)10.1049/iet-cdt:20070075 (DOI)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    6. An ASIC Perspective on High Performance FPGA Design
    Open this publication in new window or tab >>An ASIC Perspective on High Performance FPGA Design
    2009 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16564 (URN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
  • 6.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Karlström, Per
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA2008In: International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008, p. 599-602Conference paper (Refereed)
    Abstract [en]

    As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. The core can operate at 357 MHz, which is significantly faster than Xilinxpsila Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining sufficient functionality for a high performance processor.

  • 7.
    Ehliar, Andreas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Comparison of Three FPGA Optimized NoC Architectures2007In: Swedish System-on-Chip Conference, SSoCC,2007, 2007Conference paper (Other academic)
  • 8.
    Ehliar, Andreas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Network on Chip based gigabit Ethernet router implemented on an FPGA2006In: SSoCC Swedish System-on-Chip Conference,2006, 2006Conference paper (Other academic)
  • 9.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    An Asic Perspective on FPGA Optimizations2009In: 19th International Conference on Field Programmable Logic and Applications (FPL), 2009, p. 218-223Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

  • 10.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering.
    Liu, Dake
    Linköping University, Department of Electrical Engineering.
    An ASIC Perspective on High Performance FPGA Design2009Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

  • 11.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    An FPGA based Open Source Network-on-chip Architecture2007In: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, IEEE , 2007, p. 800-803Conference paper (Refereed)
    Abstract [en]

    Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

  • 12.
    Ehliar, Andreas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Benchmarking network processors2004In: Swedish System-on-Chip Conference,2004, 2004Conference paper (Other academic)
  • 13.
    Ehliar, Andreas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Flexible Route Lookup Using Range Search2005In: The Third IASTED International Conference on Communications and Computer Networks,2005, 2005Conference paper (Refereed)
  • 14.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Thinking outside the flow: Creating customized backend tools for Xilinx based designs2007In: 4th annual FPGAworld Conference, Stockholm, 2007, 2007Conference paper (Refereed)
    Abstract [en]

    This paper is intended to serve as an introduction to how to build a customized backend tool for a Xilinx based design flow. A Python based library called PyXDL is presented which allows a user to manipulate XDL files which contain a placed and routed design. Three different tools are presented which uses this library, ranging from a simple resource utilization viewer to a tool which will insert a logic analyzer into an already routed design, thus avoiding a costly complete rerun of the place and route tool.

  • 15.
    Ehliar, Andreas
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Siverskog, Jacob
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Using Partial Reconfigurability to aid Debugging of FPGA Designs2011Conference paper (Refereed)
    Abstract [en]

    This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.

  • 16.
    Ehliar, Andreas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wiklund, Daniel
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Feasibility study of a core router based on a network on chip2005In: Swedish System on Chip Conference SSoCC,2005, 2005Conference paper (Other academic)
    Abstract [en]

    In this paper we investigate the feasibility of creating a core router based upon a network on chip. The investigated architecture uses 16x10-Gbit Ethernet ports. The purpose of this is to show that it is possible to create such a solution considering current process technologies. This is done through an analysis of the required chip area, clock frequencies, and pin count. The results show that such a solution is feasible and can be implemented as a single chip.

  • 17.
    Eilert, Johan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Using low precision floating point numbers to reduce memory cost for MP3 decoding2004In: International Workshop on Multimedia Signal Processing, IEEE Xplore , 2004, p. 119-122Conference paper (Refereed)
    Abstract [en]

    The purpose of our work has been to evaluate the practicality of using a 16-bit floating point representation to store the intermediate sample values and other data in memory during the decoding of MP3 bit streams. A floating point number representation offers a better trade-off between dynamic range and precision than a fixed point representation for a given word length. Using a floating point representation means that smaller memories can be used which leads to smaller chip area and lower power consumption without reducing sound quality. We have designed and implemented a DSP processor based on 16-bit floating point intermediate storage. The DSP processor is capable of decoding all MP3 bit streams at 20 MHz and this has been demonstrated on an FPGA prototype.

  • 18.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Ehliar, Andreas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Design of a Floating Point DSP for Full Precision MPEG-I Layer II and III Decoding2005In: Swedish System on Cihip Conference SSoCC,2005, 2005Conference paper (Other academic)
  • 19.
    Garrido, Mario
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Acevedo, Miguel
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Challenging the Limits of FFT Performance on FPGAs2014Conference paper (Refereed)
    Abstract [en]

    This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT generation tool has been developed. This tool is highly parameterizable and allows for generating FFTs with different FFT sizes and amount of parallelization. Experimental results for FFT sizes from 16 to 65536, and 4 to 64 parallel samples have been obtained. They show that even the largest FFT architectures fit well in today's FPGAs, achieving throughput rates from several GSamples/s to tens of GSamples/s.

  • 20.
    Gustafsson, Oscar
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Low-complexity general FIR filters based on Winograd's inner product algorithm2013Conference paper (Other academic)
  • 21.
    Gustavsson, Mikael
    et al.
    SP Devices AB.
    Ul Amin, Farooq
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Bjorklid, Anders
    SP Devices AB.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Xu, Cheng
    Royal Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography2012In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 59, no 1, p. 30-39Article in journal (Refereed)
    Abstract [en]

    We describe a high-rate energy-resolving photon-counting ASIC aimed for spectral computed tomography. The chip has 160 channels and 8 energy bins per channel. It demonstrates a noise level of ENC= electrons at 5 pF input load at a power consumption of andlt;5mW/channel. Maximum count rate is 17 Mcps at a peak time of 40 ns, made possible through a new filter reset scheme, and maximum read-out frame rate is 37 kframe/s.

  • 22.
    Karlström, Per
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 42008In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, p. 305-313Article in journal (Refereed)
    Abstract [en]

    There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

  • 23.
    Karlström, Per
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 42006In: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, p. 31-34Conference paper (Refereed)
    Abstract [en]

    Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

  • 24.
    Olausson, Mikael
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Reduced floating point for MPEG1/2 layer III decoding2004In: IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004, p. V-209-12 vol.5-Conference paper (Refereed)
    Abstract [en]

    A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually, new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementations we can use this 16-bit floating point easily. In addition, this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model have been completed.

  • 25.
    Wiklund, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Ehliar, Andreas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Design of an internet core router using the SoCBUS network on chip2005In: International Symposium on Signals, Circuits, and Systems ISSCS,2005, 2005Conference paper (Refereed)
  • 26.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Karlström, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Ehliar, Andreas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Media DSP: An Application Specific Heterogeneous Multiprocessor SoC2006In: SSoCC Swedish System-on-Chip Conference,2006, 2006Conference paper (Other academic)
1 - 26 of 26
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