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  • 1.
    Asghar, Rizwan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wu, Di
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding2010In: Journal of Signal Processing Systems for Signal, Image, and Video Technology, ISSN 1939-8018, Vol. 60, no 1, p. 15-29Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used indifferent standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.

  • 2.
    Asghar, Rizwan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Wu, Di
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution2009In: 12th EUROMICRO Conference on Digital System Design, 2009, p. 699-706Conference paper (Refereed)
    Abstract [en]

    HSPA evolution has raised the throughput requirements for WCDMA based systems where turbo code has been adapted to perform the error correction. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithm used in WCDMA based systems does not freely allows to use them due to high percentage of memory conflicts. This paper provides a comprehensive analysis for reduction of interleaver memory conflicts while generating more than one address in a single clock cycle. It also provides trade-off analysis in terms of area and power efficiency for multiple architectures for different functions involved in the interleaver design. The final architecture supports processing of two parallel SISO blocks and manages the conflicts by applying different approaches like stream misalignment, memory division and small FIFO buffer. The proposed architecture is low cost and consumes 4.3K gates at a frequency of 150MHz. This work also focuses on reduction of pre-processing overheads by introducing the segment based modulo computation, thus providing further relaxation to SISO decoding process.

  • 3.
    Di, Wu
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nilsson, Anders
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Tell, Eric
    Coresonic AB, Linköping.
    Alfredsson, Erik
    Coresonic AB, Linköping.
    System Architecture for 3GPP LTE Modem Using a Programmable Baseband Processo2009In: International Symposium on System-on-Chip (SoC 2009), 2009Conference paper (Refereed)
    Abstract [en]

    3G evolution towards HSPA and LTE is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.

  • 4.
    Ehliar, Andreas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Comparison of Three FPGA Optimized NoC Architectures2007In: Swedish System-on-Chip Conference, SSoCC,2007, 2007Conference paper (Other academic)
  • 5.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    ASIP for Wireless Communication and Media2010Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    While general purpose processors reach both high performance and high application flexibility, this comes at a high cost in terms of silicon area and power consumption. In systems where high application flexibility is not required, it is possible to trade off flexibility for lower cost by tailoring the processor to the application to create an Application Specific Instruction set Processor (ASIP) with high performance yet low silicon cost.

    This thesis demonstrates how ASIPs with application specific data types can provide efficient solutions with lower cost. Two examples are presented, an audio decoder ASIP for audio and music processing and a matrix manipulation ASIP for MIMO radio baseband signal processing.

    The audio decoder ASIP uses a 16-bit floating point data type to reduce the size of the data memory to about 60% of other solutions that use a 32-bit data type. Since the data memory occupies a major part of the silicon area, this has a significant impact on the total silicon area, and thereby also the static and dynamic power consumption. The data width reduction can be done without any noticeable artifacts in the decoded audio due to the natural masking effect ofthe human ear.

    The matrix manipulation SIMD ASIP is designed to perform various matrix operations such as matrix inversion and QR decomposition of small complex-valued matrices. This type of processing is found in MIMO radio baseband signal processing and the matrices are typically not larger than 4x4. There have been solutions published that use arrays of fixed-function processing elements to perform these operations, but the proposed ASIP performs the computations in less time and with lower hardware cost.

    The matrix manipulation ASIP data path uses a floating point data type to avoid data scaling issues associated with fixed point computations, especially those related to division and reciprocal calculations, and it also simplifies the program control flow since no special cases for certain inputs are needed which is especially important for SIMD architectures.

    These two applications were chosen to show how ASIPs can be a suitable alternative and match the requirements for different types of applications, to provide enough flexibility and performance to support different standards and algorithms with low hardware cost.

    List of papers
    1. Using low precision floating point numbers to reduce memory cost for MP3 decoding
    Open this publication in new window or tab >>Using low precision floating point numbers to reduce memory cost for MP3 decoding
    2004 (English)In: International Workshop on Multimedia Signal Processing, IEEE Xplore , 2004, p. 119-122Conference paper, Published paper (Refereed)
    Abstract [en]

    The purpose of our work has been to evaluate the practicality of using a 16-bit floating point representation to store the intermediate sample values and other data in memory during the decoding of MP3 bit streams. A floating point number representation offers a better trade-off between dynamic range and precision than a fixed point representation for a given word length. Using a floating point representation means that smaller memories can be used which leads to smaller chip area and lower power consumption without reducing sound quality. We have designed and implemented a DSP processor based on 16-bit floating point intermediate storage. The DSP processor is capable of decoding all MP3 bit streams at 20 MHz and this has been demonstrated on an FPGA prototype.

    Place, publisher, year, edition, pages
    IEEE Xplore, 2004
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-16559 (URN)10.1109/MMSP.2004.1436435 (DOI)0-7803-8578-0 (ISBN)
    Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
    2. Efficient Complex Matrix Inversion for MIMO Software Defined Radio
    Open this publication in new window or tab >>Efficient Complex Matrix Inversion for MIMO Software Defined Radio
    2007 (English)In: International Symposium on Circuits and Systems, ISCAS,2007, IEEE , 2007, p. 2610-2613Conference paper, Published paper (Refereed)
    Abstract [en]

    Complex matrix inversion is a very computationally demanding operation in advanced multi-antenna wireless communications. Traditionally, systolic array-based QR decomposition (QRD) is used to invert large matrices. However, the matrices involved in MIMO baseband processing in mobile handsets are generally small which means QRD is not necessarily efficient. In this paper, a new method is proposed using programmable hardware units which not only achieves higher performance but also consumes less silicon area. Furthermore, the hardware can be reused for many other operations such as complex matrix multiplication, filtering, correlation and FFT/IFFT.

    Place, publisher, year, edition, pages
    IEEE, 2007
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-39855 (URN)10.1109/ISCAS.2007.377850 (DOI)51537 (Local ID)1-4244-0920-9 (ISBN)51537 (Archive number)51537 (OAI)
    Conference
    nternational Symposium on Circuits and Systems (ISCAS 2007), 27-20 May, New Orleans, Louisiana, USA
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04
    3. Complexity Reduction of Matrix Manipulation for Multi-User STBC-MIMO Decoding
    Open this publication in new window or tab >>Complexity Reduction of Matrix Manipulation for Multi-User STBC-MIMO Decoding
    Show others...
    2007 (English)In: IEEE Sarnoff Symmposium,2007, 2007, p. 1-5Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions significantly reduce the number of operations which makes them more than 4 times faster than several other solutions in the literature. Furthermore, compared to fixed function VLSI implementations, our solution is more flexible and consumes less silicon area because the hardware is programmable and it can be reused for many other operations such as filtering, correlation and FFT/IFFT. Besides the analysis of the general computational complexity based on the number of basic operations, the computational latency is also measured in clock cycles based on the conceptual hardware for real-time matrix manipulations.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-39861 (URN)10.1109/SARNOF.2007.4567354 (DOI)51543 (Local ID)978-1-4244-2483-2 (ISBN)51543 (Archive number)51543 (OAI)
    Conference
    Sarnoff Symposium, April 30-May 2, Nassau Inn, Princeton, NJ, USA
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04
    4. Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM
    Open this publication in new window or tab >>Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM
    2008 (English)In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP,2008, IEEE , 2008, p. 5396-5399Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a linear minimum mean square error (LMMSE) symbol detector for MIMO-OFDM enabled mobile terminals. The detector is implemented using a programmable baseband processor aimed for software-defined radio (SDR). Owing to the dynamic range supplied by the floating-point SIMD datapath, special algorithms can be adopted to reduce the computational latency of detection. The programmable solution not only supports different transmit/receive antenna configurations, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional solutions, the one proposed in this paper is smaller, more flexible and faster.

    Place, publisher, year, edition, pages
    IEEE, 2008
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-42734 (URN)10.1109/ICASSP.2008.4518880 (DOI)68460 (Local ID)978-1-4244-1483-3 (ISBN)68460 (Archive number)68460 (OAI)
    Conference
    IEEE International Conference on Acoustics, Speech and Signal Processing, March 31-April 4, Las Vegas, NV, USA
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04Bibliographically approved
    5. Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor
    Open this publication in new window or tab >>Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor
    2008 (English)Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a space-time block coding decoder for MIMO-OFDM enabled mobile terminals. The decoder is implemented using a programmable baseband processor aimed for software-defined radio (SDR). The dynamic range supplied by the floating-point SIMD datapath allows special algorithms to significantly reduce the computational latency of decoding. The programmable solution not only supports different transmit/receive antenna configuration, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional ASIC solutions in literature, the one proposed in this paper is by far the smallest, fastest and with more flexibility.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-42763 (URN)10.1109/ICCSC.2008.65 (DOI)68620 (Local ID)978-1-4244-1707-0 (ISBN)68620 (Archive number)68620 (OAI)
    Conference
    4th IEEE International Conference on Circuits and Systems for Communications, 26-28 May, Shanghai, China
    Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04Bibliographically approved
  • 6.
    Eilert, Johan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Using low precision floating point numbers to reduce memory cost for MP3 decoding2004In: International Workshop on Multimedia Signal Processing, IEEE Xplore , 2004, p. 119-122Conference paper (Refereed)
    Abstract [en]

    The purpose of our work has been to evaluate the practicality of using a 16-bit floating point representation to store the intermediate sample values and other data in memory during the decoding of MP3 bit streams. A floating point number representation offers a better trade-off between dynamic range and precision than a fixed point representation for a given word length. Using a floating point representation means that smaller memories can be used which leads to smaller chip area and lower power consumption without reducing sound quality. We have designed and implemented a DSP processor based on 16-bit floating point intermediate storage. The DSP processor is capable of decoding all MP3 bit streams at 20 MHz and this has been demonstrated on an FPGA prototype.

  • 7.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Ehliar, Andreas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Design of a Floating Point DSP for Full Precision MPEG-I Layer II and III Decoding2005In: Swedish System on Cihip Conference SSoCC,2005, 2005Conference paper (Other academic)
  • 8.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Early Exploratioin of MIPS Cost and Memory Cost Trade-off for Media DSP Media Processor2006In: SSoCC Swedish System-on-Chip Conference,2006, 2006Conference paper (Other academic)
  • 9.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wu, Di
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Efficient Complex Matrix Inversion for MIMO Software Defined Radio2007In: International Symposium on Circuits and Systems, ISCAS,2007, IEEE , 2007, p. 2610-2613Conference paper (Refereed)
    Abstract [en]

    Complex matrix inversion is a very computationally demanding operation in advanced multi-antenna wireless communications. Traditionally, systolic array-based QR decomposition (QRD) is used to invert large matrices. However, the matrices involved in MIMO baseband processing in mobile handsets are generally small which means QRD is not necessarily efficient. In this paper, a new method is proposed using programmable hardware units which not only achieves higher performance but also consumes less silicon area. Furthermore, the hardware can be reused for many other operations such as complex matrix multiplication, filtering, correlation and FFT/IFFT.

  • 10.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wu, Di
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM2008In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP,2008, IEEE , 2008, p. 5396-5399Conference paper (Refereed)
    Abstract [en]

    This paper presents a linear minimum mean square error (LMMSE) symbol detector for MIMO-OFDM enabled mobile terminals. The detector is implemented using a programmable baseband processor aimed for software-defined radio (SDR). Owing to the dynamic range supplied by the floating-point SIMD datapath, special algorithms can be adopted to reduce the computational latency of detection. The programmable solution not only supports different transmit/receive antenna configurations, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional solutions, the one proposed in this paper is smaller, more flexible and faster.

  • 11.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wu, Di
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor2008Conference paper (Refereed)
    Abstract [en]

    This paper presents a space-time block coding decoder for MIMO-OFDM enabled mobile terminals. The decoder is implemented using a programmable baseband processor aimed for software-defined radio (SDR). The dynamic range supplied by the floating-point SIMD datapath allows special algorithms to significantly reduce the computational latency of decoding. The programmable solution not only supports different transmit/receive antenna configuration, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional ASIC solutions in literature, the one proposed in this paper is by far the smallest, fastest and with more flexibility.

  • 12.
    Eilert, Johan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wu, Di
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wang, Dandan
    Al-Dhahir, Naofal
    Minn, Hlaing
    Complexity Reduction of Matrix Manipulation for Multi-User STBC-MIMO Decoding2007In: IEEE Sarnoff Symmposium,2007, 2007, p. 1-5Conference paper (Refereed)
    Abstract [en]

    This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions significantly reduce the number of operations which makes them more than 4 times faster than several other solutions in the literature. Furthermore, compared to fixed function VLSI implementations, our solution is more flexible and consumes less silicon area because the hardware is programmable and it can be reused for many other operations such as filtering, correlation and FFT/IFFT. Besides the analysis of the general computational complexity based on the number of basic operations, the computational latency is also measured in clock cycles based on the conceptual hardware for real-time matrix manipulations.

  • 13.
    Liu, Dake
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nilsson, Anders
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Bridging Dream and Reality: Programmable Baseband Processors for Software-Defined Radio2009In: IEEE COMMUNICATIONS MAGAZINE, ISSN 0163-6804, Vol. 47, no 9, p. 134-140Article in journal (Refereed)
    Abstract [en]

    A programmable radio baseband signal processor is one of the essential enablers of software-defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.

  • 14.
    Olausson, Mikael
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ehliar, Andreas
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Reduced floating point for MPEG1/2 layer III decoding2004In: IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004, p. V-209-12 vol.5-Conference paper (Refereed)
    Abstract [en]

    A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually, new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementations we can use this 16-bit floating point easily. In addition, this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model have been completed.

  • 15. Wang, Qi
    et al.
    Wu, Di
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio2008In: WCNC 2008: IEEE WIRELESS COMMUNICATIONS & NETWORKING CONFERENCE, IEEE , 2008, p. 935-939Conference paper (Refereed)
    Abstract [en]

    Channel State Information (CSI) is critical for the overall performance or wireless systems. Meanwhile, the estimation or CSI forms one or the most intensive tasks in radio baseband signal processing. This paper investigates the real-time implementation or channel estimation for MIMO-OFDM systems using programmable hardware aimed for software defined radio. Based on the programmable hardware architecture proposed by us, several prevalent channel estimation methods such as Least Square (LS), Minimum Mean Square Error (MMSE) and Pilot-Symbol-Aided (PSA) are evaluated from both the performance and computational latency perspectives. By utilizing the symmetric feature of the covariance matrix, a simplified two-sided Jacobi rotation method is adopted to speed up the complex-valued singular value decomposition involved in the MMSE channel estimation.

  • 16.
    Wu, Di
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Asghar, Rizwan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless2010In: EURASIP Journal on Wireless Communications and Networking, ISSN 1687-1472, E-ISSN 1687-1499, Vol. 2010, no 893184Article in journal (Refereed)
    Abstract [en]

    This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO) detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  • 17.
    Wu, Di
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Asghar, Rizwan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Ge, Qun
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    VLSI Implementation of A Multi-Standard MIMO Symbol Detector for 3GPP LTE and WiMAX2010In: Wireless Telecommunications Symposium (WTS), 2010, IEEE , 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper, a low-complexity symbol detector is presentedtargeting the emerging 3GPP LTE andWiMAX standards. The detector isthe VLSI implementation of a novel MIMO detection algorithm recentlyproposed. Compared to the design in the reference, the detector performsbetter while consumes less silicon area. Including a microcode controlledchannel preprocessing unit and a pipelined detection unit, it is flexibleenough to cover different standards and transmission schemes whilemaintaining the power and area efficiency. Implemented using 65 nmCMOS process, the detector can support real-time detection of 20 MHzbandwidth 3GPP LTE or 10 MHz WiMAX downlink physical channel.

  • 18.
    Wu, Di
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Asghar, Rizwan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Nilsson, A.
    Coresonic AB, Sweden.
    Tell, E.
    Coresonic AB, Sweden.
    Alfredsson, E.
    Coresonic AB, Sweden.
    System architecture for 3GPP-LTE modem using a programmable baseband processor2010In: International Journal of Embedded and Real-Time Communication Systems, ISSN 1947-3176, E-ISSN 1947-3184, Vol. 1, no 3, p. 44-64Article in journal (Refereed)
    Abstract [en]

    The evolution of third generation mobile communications toward high-speed packet access and long-term evolution is ongoing and will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier de-mapping. The throughput and latency requirements of a Category four User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ, which brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution. Copyright © 2010, IGI Global.

  • 19.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    A Programmable Lattice-Reduction Aided Detector for MIMO-OFDMA2008In: 4th IEEE International Conference on Circuits and Systems, ICCSC,2008, IEEE , 2008, p. 293-297Conference paper (Refereed)
    Abstract [en]

    This paper presents the first programmable Lattice- Reduction Aided (LRA) symbol detector for Multiple-Input Multiple-Output (MIMO) and Orthogonal Frequency Division Multiple Access (OFDMA). The detector proposed is implemented using 65 nm ASIC technologies. Owing to the programmability, the detector can be dynamically switched between linear (e.g. MMSE) and lattice-reduction aided (e.g. LRA-MMSE) detectors by simply running another software subroutine. Therefore, it allows a good trade-off between performance and computational latency to be achieved under various scenarios. Along with the hardware, two algorithm simplifications (SCNT-LR and SOT-LR) are proposed for finding subcarriers with ill- conditioned channel matrices. And in the end, interpolated LR (I- LR) is proposed to further reduce the computational complexity for real-time implementations.

  • 20.
    Wu, Di
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Evaluation of MIMO Symbol Detectors for 3GPP LTE Terminals2009In: 17th European Signal Processing Conference (EUSIPCO), 2009Conference paper (Refereed)
    Abstract [en]

    This paper investigates various MIMO detection methods for 3GPP LTE open-loop downlink multi-antenna transmission. Targeting VLSI implementation, these detection methods are evaluated with respect to complexity and detection performance. A realistic 3GPP LTE simulation chain is developed for the evaluation. The result shows that with the aid of Hybrid Automatic Repeat reQuest (H-ARQ), a recently proposed reduced complexity close-ML detector called MFCSO achieves a good tradeoff between achievable throughput and complexity. An adaptive transmission and detection scheme is also proposed based on user scenarios.

  • 21.
    Wu, Di
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Eilert, Johan
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio2011In: Journal of Signal Processing Systems, ISSN 1939-8115, Vol. 63, no 1, p. 27-37Article in journal (Refereed)
    Abstract [en]

    This paper presents a programmable MMSE soft-output MIMO symbol detector that supports 600 Mbps data rate defined in 802.11n. The detector is implemented using a multi-core floating-point processor and configurable soft-bit demapper. Owing to the dynamic range supplied by the floating-point SIMD datapath, special algorithms can be adopted to reduce the computational latency of channel processing with sufficient numerical stability for large channel matrices. When compared to several existing fixed-functional solutions, the detector proposed in this paper is smaller and faster. More important, it is programmable and configurable so that it can support various MIMO transmission schemes defined by different standards.

  • 22.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Lattice-Reduction Aided Multi-User STBC Decoding with Resource Constraints2007In: 2007 IEEE 18TH INTERNATIONAL SYMPOSIUM ON PERSONAL, INDOOR AND MOBILE RADIO COMMUNICATIONS, IEEE , 2007, p. 192-196Conference paper (Refereed)
    Abstract [en]

    Recently lattice-reduction aided decoders have been proposed in MIMO system to achieve near Maximum Likelihood decoder performance while maintaining reasonable complexity. This paper studies the implementation of lattice-reduction aided linear decoders on a programmable device for multi-user space-time block coding (MU-STBC). By reloading software, the device can be configured to use different decoding schemes according to the amount of resources available, which is an important feature of cognitive radio. In this paper, two different lattice-reduction aided linear decoding methods namely SQRD-LR and AQRD-LR for MU-STBC are evaluated based on their BER performance and computational complexity. Furthermore, the effect of deadline constraint on LR is evaluated and based on the evaluation, a new method namely adaptive decoding is proposed by us to allow mode-switching of the decoder according to the environment parameters, so that the best decoder performance can always be achieved while fulfiling the resource constraints.

  • 23.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Wang, Dandan
    Al-Dhahir, Naofal
    Minn, Hlaing
    Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding2007In: IEEE Computer Society Annual Aymposium on VLSI, ISVLSI,2007, IEEE , 2007, p. 325-330Conference paper (Refereed)
    Abstract [en]

    This paper studies the efficient complex matrix inversion for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) and its programmable VLSI implementation are proposed for the inversion of (in this context) large complex matrices with Alamouti sub-blocks. Our solution significantly reduces the number of operations which makes it more than 4 times faster than several other solutions in the literature. Furthermore, compared to these fixed function VLSI implementations, our solution is more flexible and consumes less silicon area because the hardware can be reused for many other operations. In addition to the routine analysis of the general computational complexity based on the number of basic operations, the computational latency is also measured in clock cycles based on the conceptual hardware for real-time matrix inversion.

  • 24.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Karlström, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Ehliar, Andreas
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Media DSP: An Application Specific Heterogeneous Multiprocessor SoC2006In: SSoCC Swedish System-on-Chip Conference,2006, 2006Conference paper (Other academic)
  • 25.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Li, Yi-Hsien
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Real-Time Space-Time Adaptive Processing on the STI CELL Multiprocessor2007In: 4th European Radar Conference,2007, IEEE , 2007, p. 71-74Conference paper (Refereed)
    Abstract [en]

    Space-time adaptive processing (STAP) has been widely used in modern radar systems such as ground moving target indication (GMTI) systems in order to suppress jamming and interference. However, its baseband signal processing part usually requires huge amount of computing power. This paper presents the real-time implementation of an STAP baseband signal processing flow on the state-of-the-art STI CELL multiprocessor which enables the concept of software-defined radar (SDR). SIMD vectorization is applied to speed-up the kernel subroutines of STAP such as the QR decomposition, forward/backward substitution and fast Fourier transform (FFT). Benchmarking results of both the kernel subroutines and the overall flow are presented. Furthmore, based on the result of earlier benchmarking, optimized task partitioning and scheduling methods are proposed by us to improve the overall performance so that the overhead is reduced to the minimum.

  • 26.
    Wu, Di
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Lim, Boonshyang
    Eilert, Johan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Liu, Dake
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Parallelization of High-Performance Video Encoding on a Single-Chip Multiprocessor2007In: IEEE International Conference on Signal Processing and Communications,2007, IEEE , 2007Conference paper (Refereed)
    Abstract [en]

    Although single-chip multiprocessor architectures are available nowadays for embedded computing, programming them with efficiency and productivity has become a significant challenge. This paper studies the multi-level parallelization of video encoding algorithms on a state-of-the-art on-chip multiprocessor. The encoding of H.264/AVC video is chosen as the case to be studied because of its performance demanding and branch-rich features. The final benchmarking result proves that the optimized processing flow can achieve more than 100 operations per cycle in performance which allows a single-chip multiprocessor to encode high resolution video (1920 x 1080) in real-time (30 fps).

1 - 26 of 26
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