liu.seSearch for publications in DiVA
Change search
Refine search result
1 - 37 of 37
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Qureshi, Fahad
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ullah Sheikh, Zaka
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Comparison of Multiplierless Implementation of Nonlinear-Phase Versus Linear-Phase FIR filters2008Conference paper (Refereed)
    Abstract [en]

    FIR filters are often used because of their linear-phase response. However, there are certain applications where the linear-phase property is not required, such as signal energy estimation, but IIR filters can not be used due to the limitation of sample rate imposed by the recursive algorithm. In this work, we discuss multiplierless implementation of minimum order, and therefore nonlinear-phase, FIR filters and compare it to the linear-phase counterpart.

  • 2.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, Andrew
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Macleod, Malcolm
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Simplified Design of Constant Coefficient Multipliers2006In: Circuits, systems, and signal processing, ISSN 0278-081X, E-ISSN 1531-5878, Vol. 25, no 2, p. 225-251Article in journal (Refereed)
    Abstract [en]

    In many digital signal processing algorithms, e.g., linear transforms and digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work two approaches to realize constant coefficient multiplication with few adders and subtracters are presented. The first yields optimal results, i.e., a minimum number of adders and subtracters, but requires an exhaustive search. Compared with previous optimal approaches, redundancies in the exhaustive search cause the search time to be drastically decreased. The second is a heuristic approach based on signed-digit representation and subexpression sharing. The results for the heuristic are worse in only approximately 1% of all coefficients up to 19 bits. However, the optimal approach results in several different optimal realizations, from which it is possible to pick the best one based on other criteria. Relations between the number of adders, possible coefficients, and number of cascaded adders are presented, as well as exact equations for the number of required full and half adder cells. The results show that the number of adders and subtracters decreases on average 25% for 19-bit coefficients compared with the canonic signed-digit representation.

  • 3.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    An empirical study on standard cell synthesis of elementary function look-up tables2008In: Conference Record - Asilomar Conference on Signals, Systems and Computers, Piscataway, NJ: IEEE , 2008, p. 1810-1813Conference paper (Refereed)
    Abstract [en]

    When hardware for implementing elementary functions is discussed it is often stated that for "small enough" tables it is possible to just synthesize the HDL description to standard cells. In this work we investigate this fact and show that the resulting cell area primarily depends on the smallest of the number of input and output bits, while the contribution of the larger of the two bit-widths is significantly smaller.

  • 4.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multiplierless piecewise linear approximation of elementary functions2006In: Asilomar Conference on Signals, Systems, and Computers,2006, Piscataway: IEEE , 2006Conference paper (Refereed)
  • 5.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation of polyphase decomposed FIR filters for interpolation and decimation using multiple constant multiplication techniques2006In: IEEE Asia Pacific Conference on Circuits and Systems,2006, Piscataway: IEEE , 2006, p. 924-927Conference paper (Refereed)
    Abstract [en]

    Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. Almost all work has been focused on single rate FIR filters. However, for polyphase interpolation and decimation FIR filters there are two different implementation alternatives. For interpolation, direct form subfilters lead to fewer registers as they can be shared among the subfilters. The arithmetic part corresponds to a matrix vector multiplication. Using transposed direct form subfilters, the registers can not be shared, while the arithmetic part has the same input to all coefficients, and, hence, the redundancy between the coefficients is expected to be higher. For decimation filters the opposite holds for direct form and transposed direct form subfilters. In this work we discuss the trade-off between adders/subtracters and registers, and present implementation results for area, speed, and power for different realizations

  • 6.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Optimization and Quantization Effects for Sine and Cosine Computation Using a Sum of Bit-Products2005In: Asilomar Conference on Signals, Systems, and Computers,2005, Piscataway, NJ: IEEE , 2005, p. 1347­-Conference paper (Refereed)
    Abstract [en]

    Recently, a novel technique to compute sine and cosine has been proposed. By rewriting the expressions using trigonometric equations a weighted sum of bit-products is used to compute the values. This can then be mapped onto a bit-product generator followed by an adder tree. This provides an efficient architecture that can be pipelined to an arbitrary degree. It was shown in previous work that it is possible to remove a large portion of the bit-products and still obtain accurate results. The objective of this work is to study the effects of this removal and also the finite wordlength representation of the weights. Furthermore, optimization problems are formulated that can be used to minimize the maximum absolute error, the average absolute error, and the mean square error for the output values, respectively, as well as implementation complexity under error constraints.

  • 7.
    Gustafsson, Oscar
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Tahmasbi Oskuii, Saeeid
    Department of Electronics and Telecommunications Norwegian University of Science and Technology NTNU.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Kjeldsberg, Per Gunnar
    Department of Electronics and Telecommunications Norwegian University of Science and Technology NTNU.
    Switching activity reduction of MAC-based FIR filters with correlated input data2007In: International Workshop on Power and Timing Modeling, Optimization and Simulation,2007, Heidelberg: Springer , 2007, p. 526-Conference paper (Refereed)
  • 8.
    Johansson, Håkan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Adjustable fractional-delay FIR filters using the Farrow structure and multirate techniques2006In: Asia Pacific Conference on Circuits and Systems,2006, 2006, p. 1055-1058Conference paper (Refereed)
    Abstract [en]

    The Farrow structure can be used for efficient realization of adjustable fractional-delay finite-length impulse response (FIR) filters, but, nevertheless, its implementation complexity grows rapidly as the bandwidth approaches the full bandwidth. To reduce the complexity, a multirate approach can be used. In this approach, the input signal is first interpolated by a factor of two via the use of a fixed half-band linearphase FIR filter. Then, the actual fractional-delay filtering takes place. Finally, the so generated signal is downsampled to retain the original input/output sampling rate. In this way, the bandwidth of the fractional-delay filter used is halved compared to the overall bandwidth. Because the complexity of halfband linear-phase FIR filter interpolators is low, the overall complexity can be reduced. In this paper, we present more implementation details, design trade-offs, and comparisons when the filters are implemented using multiple constant multiplication techniques, which realize a number of constant multiplications with a minimum number of adders and subtracters.

  • 9.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low Power and Low complexity Constant Multiplication using Serial Arithmetic2006Licentiate thesis, monograph (Other academic)
    Abstract [en]

    The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplication using serial arithmetic. The possibility to reduce the complexity and energy consumption is investigated. The main difference between serial and parallel arithmetic, which is of interest here, is that a shift operation in serial arithmetic require a flip-flop, while it can be hardwired in parallel arithmetic.

    The possible ways to connect a certain number of adders is limited, i.e., for single-constant multiplication, the number of possible structures is limited for a given number of adders. Furthermore, for each structure there is a limited number of ways to place the shift operations. Hence, it is possible to find the best solution for each constant, in terms of complexity, by an exhaustive search. Methods to bound the search space are discussed. We show that it is possible to save both adders and shifts compared to CSD serial/parallel multipliers. Besides complexity, throughput is also considered by defining structures where the critical path, for bit-serial arithmetic, is no longer than one full adder.

    Two algorithms for the design of multiple-constant multiplication using serial arithmetic are proposed. The difference between the proposed design algorithms is the trade-offs between adders and shifts. For both algorithms, the total complexity is decreased compared to an algorithm for parallel arithmetic.

    The impact of the digit-size, i.e., the number of bits to be processed in parallel, in FIR filters is studied. Two proposed multiple-constant multiplication algorithms are compared to an algorithm for parallel arithmetic and separate realization of the multipliers. The results provide some guidelines for designing low power multiple-constant multiplication algorithms for FIR filters implemented using digit-serial arithmetic.

    A method for computing the number of logic switchings in bit-serial constant multipliers is proposed. The average switching activity in all possible multiplier structures with up to four adders is determined. Hence, it is possible to reduce the switching activity by selecting the best structure for any given constant. In addition, a simplified method for computing the switching activity in constant serial/parallel multipliers is presented. Here it is possible to reduce the energy consumption by selecting the best signed-digit representation of the constant.

    Finally, a data dependent switching activity model is proposed for ripple-carry adders. For most applications, the input data is correlated, while previous estimations assumed un-correlated data. Hence, the proposed method may be included in high-level power estimation to obtain more accurate estimates. In addition, the model can be used as cost function in multiple-constant multiplication algorithms. A modified model based on word-level statistics, which is accurate in estimating the switching activity when real world signals are applied, is also presented.

  • 10.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low Power and Low Complexity Shift-and-Add Based Computations2008Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using shift-and-add based computations. The possibilities to reduce the complexity, i.e., the chip area, and the energy consumption are investigated. Both serial and parallel arithmetic are considered. The main difference, which is of interest here, is that shift operations in serial arithmetic require flip-flops, while shifts can be hardwired in parallel arithmetic.The possible ways to connect a given number of adders is limited. Thus, for single-constant multiplication, the number of shift-and-add structures is finite. We show that it is possible to save both adders and shifts compared to traditional multipliers. Two algorithms for multiple-constant multiplication using serial arithmetic are proposed. For both algorithms, the total complexity is decreased compared to one of the best-known algorithms designed for parallel arithmetic. Furthermore, the impact of the digit-size, i.e., the number of bits to be processed in parallel, is studied for FIR filters implemented using serial arithmetic. Case studies indicate that the minimum energy consumption per sample is often obtained for a digit-size of around four bits.The energy consumption is proportional to the switching activity, i.e., the average number of transitions between the two logic levels per clock cycle. To achieve low power designs, it is necessary to develop accurate high-level models that can be used to estimate the switching activity. A method for computing the switching activity in bit-serial constant multipliers is proposed.For parallel arithmetic, a detailed complexity model for constant multiplication is introduced. The model counts the required number of full and half adder cells. It is shown that the complexity can be significantly reduced by considering the interconnection between the adders. A main factor for energy consumption in constant multipliers is the adder depth, i.e., the number of cascaded adders. The reason for this is that the switching activity will increase when glitches are propagated to subsequent adders. We propose an algorithm, where all multiplier coefficients are guaranteed to be realized at the theoretically lowest depth possible. Implementation examples show that the energy consumption is significantly reduced using this algorithm compared to solutions with fewer word level adders.For most applications, the input data are correlated since real world signals are processed. A data dependent switching activity model is derived for ripple-carry adders. Furthermore, a switching activity model for the single adder multiplier is proposed. This is a good starting point for accurate modeling of shift-and-add based computations using more adders.Finally, a method to rewrite an arbitrary function as a sum of weighted bit-products is presented. It is shown that for many elementary functions, a majority of the bit-products can be neglected while still maintaining reasonable high accuracy, since the weights are significantly smaller than the allowed error. The function approximation algorithms can be implemented using a low complexity architecture, which can easily be pipelined to an arbitrary degree for increased throughput.

  • 11.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    DeBrunner, Linda
    FAMU-FSU College of Engineering.
    Estimation of the switching activity in shift-and-add based computations2009In: IEEE International Symposium on Circuits and Systems, Piscataway, 2009, p. 3054-3057Conference paper (Refereed)
    Abstract [en]

    In this work, we propose a switching activity model for constant multipliers. The model can also be used for other architectures that are composed by full adders. Hence, the proposed model is suitable to be used in power consumption aware design algorithms. An important category is algorithms for the multiple-constant multiplication (MCM) problem. The model is shown to agree well with simulations, especially for carry-save arithmetic.

  • 12.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, A.G
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic2004In: Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference, 2004. MELECON 2004, Volume 1, IEEE , 2004, p. 197-200Conference paper (Other academic)
    Abstract [en]

    In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.

  • 13.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Dempster, Andrew
    School of Surveying Spatial Information Systems UNSW, Sydney, Australia.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Trade-offs in low power multiplier blocks using serial arithmetic2005In: National Conf. Radio Science RVK,2005, Linköping: RVK , 2005, p. 271-274Conference paper (Refereed)
    Abstract [en]

    In this paper trade-offs in multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity, logic depth, and power consumption. A new algorithm that reduces the number of shifts while the number of adders is on average the same is presented. Hence, the total complexity is reduced for multiplier blocks implemented using serial arithmetic, where shift operations has a cost. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that need to be considered is logic depth.

  • 14.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity2005In: European Conf. Circuit Theory Design,2005, Cork: IEEE , 2005, p. III/465-Conference paper (Refereed)
    Abstract [en]

    Multiple constant multiplication (MCM) has been an active research area for the last decade. Most work so far have only considered the number of additions to realize a number of constant multiplications with the same input. In this work, we consider the number of full and half adder cells required to realize those additions, and a novel complexity measure is proposed. The proposed complexity measure can be utilized for all types of constant operations based on shifts, additions and subtractions. Based on the proposed complexity measure a novel MCM algorithm is presented. Simulations show that compared with previous algorithms, the proposed MCM algorithm have a similar number of additions while the number of full adder cells are significantly reduced.

  • 15.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Approximation of elementary functions using a weighted sum of bit-products2006In: IEEE Int. Symp. Circuits Syst.,2006, Piscataway, NJ: IEEE , 2006, p. 795-Conference paper (Refereed)
    Abstract [en]

    In this work a novel approach for approximating elementary functions is presented. By rewriting the function as a sum of weighted bit-products an efficient implementation is obtained. For most functions a majority of the bit-products can be neglected and still obtain good accuracy. The method is suitable for high-speed implementation of fixed-point functions.

  • 16.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Bit-Level Optimization of Shift-and-Add Based FIR Filters2007In: IEEE International Conference on Electronics, Circuits and Systems,2007, Piscataway, NJ: IEEE , 2007, , p. 713-716p. 713-716Conference paper (Refereed)
    Abstract [en]

    Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.

  • 17.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Conversion and addition in logarithmic number systems using a sum of bit-products2006In: IEEE NorChip Conf.,2006, Linköping: IEEE , 2006, , p. 39-42p. 39-42Conference paper (Refereed)
    Abstract [en]

    Computations in logarithmic number systems require realizations of four different elementary functions. In this work we utilize a recently proposed approximation method based on weighted sums of bit-products to realize these functions. It is shown that the considered method can be used to efficiently realize the different functions. However, a transformation is proposed to improve the results for functions with logarithmic characteristics.

  • 18.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Estimation of switching activity for ripple-carry adders adopting the dual bit type method2005In: Swedish System-on-Chip Conf.,2005, Tammsvik: SSoCC , 2005Conference paper (Other academic)
    Abstract [en]

    In this work a model for estimation of the switching activity in ripple-carry adders is presented. The model is based on word-level statistics, such as mean, variance, and correlation, of the two input signals to be added. It is shown that the proposed model gives accurate results when the two-s-complement represented inputs are real world signals.

  • 19.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation of elementary functions for logarithmic number systems2008In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, no 4, p. 295-304Article in journal (Refereed)
    Abstract [en]

     Computations in logarithmic number systems require realisations of four different elementary functions. In the current paper the authors use a recently proposed approximation method based on weighted sums of bit-products to realise these functions. It is shown that the considered method can be used to efficiently realise the different functions. Furthermore, a transformation is proposed to improve the results for functions with logarithmic characteristics. Implementation results shows that significant savings in area and power can be obtained using optimisation techniques. 

  • 20.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation of low-complexity FIR filters using serial arithmetic2005In: IEEE Int. Symp. Circuits Syst.,2005, Piscataway, NJ: IEEE , 2005, p. II/1449-Conference paper (Refereed)
    Abstract [en]

    The effects of digit-size on FIR filters implemented using multiplier block techniques are studied. Two different multiplier block algorithms are considered, one that minimizes the number of adders without considering the number of shifts and one that minimizes the number of shifts while keeping the number of adders low. Results on area, sample rate, and power consumption are presented, focusing on the arithmetic parts of the FIR filter.

  • 21.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Low power architectures for sine and cosine computation using a sum of bit-products2005In: IEEE NorChip Conf.,2005, Oulu: IEEE , 2005, p. 161-Conference paper (Refereed)
    Abstract [en]

    Recently, a novel technique to compute sine and cosine has been proposed. By rewriting the expressions using trigonometric equations a weighted sum of bit-products are used to compute the values. This can then be mapped onto a bit-product generator followed by an adder tree. This provides an efficient architecture that can be pipelined to an arbitrary degree. It was shown in previous work that it is possible to remove a large portion of the bit-products and still obtain accurate results. The effects of this removal and also the finite worldlength representation of the weights has also been discussed in previous work. The objective of this work is to study different ways to split the architecture into sub-blocks that may be disabled to decrease the power consumption.

  • 22.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low-complexity bit-serial constant-coefficient multipliers2004In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 3, IEEE , 2004, p. 649-652Conference paper (Other academic)
    Abstract [en]

    In this work we investigate the possibilities to minimize the complexity of bit-serial constant-coefficient multipliers. This is done in terms of number of required building blocks, which includes adders and flip-flops. The multipliers are described using a graph representation. We show that it is possible to find a minimum set of graphs that are required to get optimal results for the different multiplier types. The complexity cost for these multipliers are then investigated. Most results are compared to multipliers that adopt the commonly used canonic signed-digit representation.

  • 23.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multiple Constant Multiplication for Digit-Serial Implementation of Low Power FIR Filters2006In: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, no 7, p. 1001-1008Article in journal (Refereed)
    Abstract [en]

    Multiple constant multiplication (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. By utilizing redundancy between the coefficients the number of adders and subtracters is reduced resulting in a low complexity implementation. However, for digit-serial arithmetic a shift requires a flip-flop, and, hence, the number of shifts should be taken into consideration as well. In this work we investigate the area, speed, power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. We also introduce an algorithm for reducing both the number of adders and subtracters as well as the number of shifts.

  • 24.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power estimation for bit-serial constant coefficient multipliers2004In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper (Other academic)
    Abstract [en]

    In this work a model for estimation of the power consumption in bit-serial, constant coefficient multipliers is presented. The multipliers are implemented using shift-add operations. Model parameters for the required components, i.e., flip-flops and full-adders, are derived. The power for a multiplier is obtained by summing the power for all components included in the corresponding network of shifts and adders.

  • 25.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power Estimation for Ripple-Carry Adders with Correlated Input Data2004In: International Workshop on Power and Timing Modeling, Optimization and Simulation,2004, 2004, p. 662-674Conference paper (Other academic)
    Abstract [en]

    In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation

  • 26.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power estimation for ripple-carry adders with correlated input data2004In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings / [ed] Enrico Macii, Vassilis Paliouras and Odysseas Koufopavlou, Springer Berlin/Heidelberg, 2004, Vol. 3254, p. 662-674Chapter in book (Refereed)
    Abstract [en]

    In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation.

  • 27.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Switching activity estimation for shift-and-add based constant multipliers2008In: IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., Piscataway, NJ: IEEE , 2008, , p. 676-679p. 676-679Conference paper (Refereed)
    Abstract [en]

    In this work we propose a switching activity model for single adder multipliers. This correspond to the case where a signal is added to a shifted version of itself, which is a common part in multiple constant multiplication (MCM). Hence, the proposed model is suitable to be used in power consumption aware MCM algorithms. The model is shown to agree well with simulations, and for the studied test cases a maximum error of 0.26% is obtained.

  • 28.
    Johansson, Kenny
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wanhammar, Lars
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Switching activity in bit-serial constant coefficient multipliers2004In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 2, IEEE , 2004, p. 469-472Conference paper (Other academic)
    Abstract [en]

    In this paper a method for computing the switching activity in bit-serial constant-coefficient multipliers is presented. The multipliers are described using a graph representation. It is shown that the average switching activity in all multipliers with up to four adders can be determined. Most of the switching activities can be obtained directly from the derived formulas and the remaining by using look-up tables. The switching activities are useful to estimate the power consumption, and makes it possible to choose the best power saving multiplier structure.

  • 29.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Switching activity in bit-serial constant coefficient serial/parallel multipliers2003In: IEEE NorChip Conf.,2003, Piscataway, NJ: IEEE , 2003, p. 260-Conference paper (Refereed)
    Abstract [en]

    In this work a method for computing the switching activity in bit-serial, constant-coefficient serial/parallel multipliers is presented. We derive a function for the switching activities, which is useful to estimate and optimise the power consumption. This makes it possible to choose a power saving coefficient representation.

  • 30.
    Johansson, Kenny
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Trade-offs in multiplier block algorithms for low power digit-serial FIR filters2006In: WSEAS Int. Conf. Circuits,2006, Athens: WSEAS , 2006Conference paper (Refereed)
    Abstract [en]

    In this paper trade-offs in digit-serial multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity and adder depth. Among the three algorithms is a new algorithm that reduces the number of shifts while the number of adders is on average the same. Hence, the total complexity is reduced for multiplier blocks implemented using digit-serial arithmetic, where shift operations have a hardware cost. An example implementation is used to compare the power consumption for five approaches: the three algorithms, using separate multipliers based on CSD representation, and an algorithm based on subexpression sharing. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that needs to be considered is adder depth. Furthermore, digit-serial shifts will reduce glitch propagation.

  • 31.
    Lindkvist, Tina
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Information Theory.
    Löfvenberg, Jacob
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Information Theory.
    Ohlsson, Henrik
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances2004In: IEEE International Workshop on System on Chip for Real-Time Applications,2004, Los Alamitos, California, USA: IEEE Computer Society , 2004, p. 257-Conference paper (Refereed)
    Abstract [en]

    In this paper we present a simplified model of parallel, on-chip buses, motivated by the movement toward CMOS technologies where the ratio between inter-wire capacitance and wire-to-ground capacitance is very large. We also introduce a ternary bus state representation, suitable for the bus model. Using this representation we propose a coding scheme without memory which reduces energy dissipation in the bus model by approximately 20-30% compared to an uncoded system. At the same time the proposed coding scheme is easy to realize, in terms of standard cells needed, compared to several previously proposed solutions.

  • 32.
    Löfvenberg, Jacob
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Information Theory.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering.
    Lindkvist, Tina
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Information Theory.
    Ohlsson, Henrik
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Coding schemes for deep sub-micron data buses2005In: Radiovetenskap och Kommunikation, RVK05,2005, 2005Conference paper (Refereed)
    Abstract [en]

    We present two coding techniques for reducing the power dissipation in deep sub-micron, parallel data buses. The techniques differ in their parameter values and are suitable in different scenarios. In both cases typical reduction in power dissipation is 20%.

  • 33.
    Ohlsson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 16 GSPS 0.18 µm CMOS decimator for single-bit ∑∆-modulation.2004In: Norchip,2004, Piscataway: IEEE Inc. , 2004, p. 175-Conference paper (Refereed)
  • 34.
    Tahmasbi Oskuii, Saeeid
    et al.
    NTNU.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Kjeldsberg, Per Gunnar
    NTNU.
    Power optimization of weighted bit-product summation tree for elementary function generator2008In: IEEE International Symposium on Circuits and Systems,2008, Piscataway, NJ: IEEE , 2008, p. 1240-Conference paper (Refereed)
  • 35.
    Wanhammar, Lars
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Efficient sine and cosine computation using a weighted sum of bit-products2005In: European Conf. Circuit Theory Design,2005, Piscataway, NJ: IEEE , 2005, p. I/139-Conference paper (Refereed)
    Abstract [en]

    An angle rotation based approach to simultaneously compute sin(x) and cos(x) is presented. The approach yields a weighted sum of bit-products of the binary bits that represent the angle x. We discuss the required number of terms in the polynomial as well as the required coefficient wordlength as function of accuracy. The approach yields a combinatorial realization with a low complexity. We also propose a corresponding fast and simple architecture. The combinatorial circuit has low latency and can easily be pipelined for a high throughput.

  • 36.
    Wanhammar, Lars
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Soltanian, B
    n/a.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Synthesis of Circulator-Tree Wave Digital Filters2007In: PROCEEDINGS OF THE 5TH INTERNATIONAL SYMPOSIUM ON IMAGE AND SIGNAL PROCESSING AND ANALYSIS, IEEE , 2007, p. 206-211Conference paper (Refereed)
    Abstract [en]

    In this paper, we show that circulator-tree wave digital filters are an interesting alternative to lattice WDFs. Furthermore, we provide two simple programs for design of lattice and circulator-tree lowpass filters and compare the two structures with respect to element sensitivity.

  • 37.
    Wanhammar, Lars
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Soltanian, Baharak
    Tampere University of Technology.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Kenny
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Synthesis of bandpass circulator-tree wave digital filters2008In: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008., Piscataway, NJ: IEEE , 2008, , p. 834-837p. 834-837Conference paper (Refereed)
    Abstract [en]

      In this paper, we discuss the design of bandpass circulator-tree wave digital filters derived from analog lowpass filters using the geometrical symmetric transformation. These structures are an interesting alternative to lattice WDFs showing a high modularity and posses the same properties as other WDF structures.

1 - 37 of 37
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf