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  • 1.
    Alvandporu, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Impact of Miller Capacitance on Power Consumption1998In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1998, p. 83-92Conference paper (Refereed)
  • 2.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Domino circuit2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage lin

  • 3.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Enhanced domino circuit2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

  • 4.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-Performance and Low-Power Challenges for Sub-70nm System on Chip. Invited talk2003In: International workshop on Circuit Design (IWCD 2004), June 17, National Taiwan University, Taipei, Taiwan, 2003Conference paper (Other academic)
  • 5.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-performance and Low-voltage Datapath and Interconnect Design Challenges2004In: In proceedings of: 12th IEEE Mediterranean Electrotechnical Conference, MELECON, 12-15 May, Dubrovnik, Croatia, 2004Conference paper (Refereed)
  • 6.
    Alvandpour, Atila
    Linköping University, Department of Physics, Measurement Technology, Biology and Chemistry. Linköping University, The Institute of Technology.
    Power Estimation and Low Power CMOS Circuit Techniques1999Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The increasing power consumption due to the high integration rate of VLSI digital CMOS circuits has become a major concern. Many important design issues and parameters are strongly dependent on the power dissipation and the accuracy of its estimated value during the design exploration. Among these issues we identify particularly the operation time per battery pack, the computational capacity and performance of the mobile electronic products, as well as more general aspects such as circuit reliability, cost for packaging and power supplies. In this thesis, some issues on power estimation and development of low-power circuit techniques, aimed for medium and high speed operations, are addressed.

    The complex impact of Miller capacitance on power and performance of digital CMOS circuits is investigated. Significant enhancements in characterization and modeling of the Miller effects compared to the existing conclusions, which are based on simplified rules, are achieved.

    A novel estimation technique for the relatively involved average short-circuit power consumption has been developed. Compared to the existing, time-consuming technique, the proposed technique provides a fast estimation with a reasonable accuracy, and has a potential to be used for real measurement.

    A significant portion of the total power consumption in VLSI circuits is due to the capacitance of the interconnections, however, estimating the interconnect length and its RC property at early stages in a large-scale top-down design flow is a hard task. Existing, simplified interconnection length estimation techniques are unacceptably inaccurate and unable to give a useful feedback during the design verification and simulation.

    A new design-sensitive interconnection length estimation technique and a corresponding algorithm has been developed. The technique has the unique quality to estimate the length of each interconnection separately, and therefore detects and localizes most of the potentially long interconnects. The result of the estimation can directly be used to add the important RC properties of the interconnects to the power estimators or circuit simulators, consequently yielding a significant increase in estimation accuracy.

    An investigation on generic low-power circuit techniques aimed for main-stream design styles has been made and various suggestions are proposed. The result has later been used to adapt the design of cell libraries to low power requirements.

    High fan-in dynamic gates can result in lower power consumption, fewer logic levels and very compact layout. Two major disadvantages, which reduce the practical use of such wide gates, are the relatively long propagation delay and the large leakage currents, which are due to the increasing subthreshold current in today's and future submicron devices. For speeding up the wide gates, new and simple sensing elements are proposed, which results in faster gates and lower power consumption compared to the alternative solutions. The issues related to large subthreshold leakage currents is also addressed and a leakage-tolerant multi-phase keeper circuit is presented. The new keeper holds the dynamic output of the wide domino gates statically, with a greater driving strength than that in the conventional solution. Furthermore, an increase in robustness is achieved without any significant delay penalty.

    Large capacitive loads resulting from long on-chip interconnects and the corresponding driver-receiver circuits can consume a significant portion of the total power consumption of a CMOS chip. A low-power, high-speed and robust driver-receiver circuit is proposed. The new bus architecture utilizes a precharge-to-low interconnect and a fast and simple level converter as receiver, which together reduce the power consumption up to 70% below that of a conventional precharged bus architecture without any delay penalty.

    List of papers
    1. Impact of Miller Capacitance on Power Consumption
    Open this publication in new window or tab >>Impact of Miller Capacitance on Power Consumption
    1998 (English)In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1998, p. 83-92Conference paper, Published paper (Refereed)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-54107 (URN)
    Available from: 2010-02-23 Created: 2010-02-23 Last updated: 2022-05-04
    2. Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits
    Open this publication in new window or tab >>Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits
    1998 (English)In: ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design, 1998, p. 245-249Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a Vdd close to VT and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low Vdd. To avoid reducing Vdd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to VT based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

    Keywords
    Short-circuit current, Power consumption, Power estimation.
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-54104 (URN)10.1145/280756.280919 (DOI)
    Conference
    International Symposium on Low-Power Electronics and Design, 10-12 August 1998, Monterey, California, USA
    Available from: 2010-02-23 Created: 2010-02-23 Last updated: 2022-05-04
    3. A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction
    Open this publication in new window or tab >>A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction
    1997 (English)In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1997, p. 305-314Conference paper, Published paper (Refereed)
    Abstract [en]

    A new wire estimation technique is presented. It utilizes the topology of the netlist and is sensitive to the actual design. It has the unique quality to estimate the length of every power consuming interconnection individually. Compared to other wire length estimation techniques which use average or total wire length, the result of the new technique shows a strong correlation with the result of "real" automatic placement and route tools. Hence it can estimate a reasonable wire capacitance for each interconnection. The individual wire lengths, combined with individual node activities, are essential for an accurate power estimation.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-54108 (URN)
    Available from: 2010-02-23 Created: 2010-02-23 Last updated: 2022-05-04
    4. Improving Cell Libraries for Low Power Design
    Open this publication in new window or tab >>Improving Cell Libraries for Low Power Design
    1996 (English)In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1996, p. 317-325Conference paper, Published paper (Refereed)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-54109 (URN)
    Available from: 2010-02-23 Created: 2010-02-23 Last updated: 2022-05-04
    5. A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits
    Open this publication in new window or tab >>A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits
    1999 (English)In: In proceedings of: IEEE International Conference on Electronics, Circuits, And System, 1999, p. 209-212Conference paper, Published paper (Refereed)
    Abstract [en]

     

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-54105 (URN)
    Available from: 2010-02-23 Created: 2010-02-23 Last updated: 2022-05-04
  • 7.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arakawa, Fumio
    Hitachi, Tokyo, Japan.
    Session 20 overview - processor building blocks2005Conference paper (Other (popular science, discussion, etc.))
  • 8.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arimoto, Kazutami
    Renesas Corp, Itami, Hyogo 6640005 Japan .
    Cantatore, Eugenio
    Eindhoven University Technology, NL-5600 MB Eindhoven, Netherlands .
    Zhang, Kevin
    Intel Corp, Hillsboro, OR 97124 USA .
    Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 1, p. 3-6Article in journal (Other academic)
    Abstract [en]

    n/a

  • 9.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Balamurugan, G.
    Intel Corp., USA.
    Soumyanath, K.
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Leakage-tolerant circuit and method for large register files2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.

  • 10.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Multi-phase clock generation and synchronization2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A method for controlling a local clock includes receiving a reference clock and generating a phase-shifted version of the reference clock. The two clocks are synchronized using a closed-loop method that produces a control signal. The control signal is smoothed during the closed-loop method and the smoothed signal is then used, instead of the control signal, in generating the phase-shifted clock

  • 11.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Intel Corporation, Hillsboro, USA.
    Borkar, S.
    Intel Corporation, Hillsboro, USA.
    Rahman, A.
    Intel Corporation, Hillsboro, USA.
    Webb, C.
    Intel Corporation, Hillsboro, USA.
    A burn-in tolerant dynamic circuit technique2002In: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, p. 81-84Conference paper (Refereed)
  • 12.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Conditional Keeper Technique for Sub-0.13mm Wide Dynamic Gates2001In: In proceedings of: International Symposium on VLSI Circuits, 2001, p. 29-30Conference paper (Refereed)
  • 13.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Sournyanath, K.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    Borkar, S.
    Microprocessor Research Labs, Intel Corporation, Hillsboro, OR .
    A Low-Leakage Dynamic Multi-Ported Register file in 0.13mm CMOS2001In: ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design, New York, USA: ACM , 2001, p. 68-71Conference paper (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256X32b 4-read/write-port Register-File for ~6GHz operation at 1.2V in a 0.13 utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned remains are able to improve upon all-low-Vt performance by 4%, while maintaining Dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5X.

     

  • 14.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Conditional burn-in keeper for dynamic circuits2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

  • 15.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Fast static receiver with input dependent inversion threshold.2006Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

  • 16.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Voltage-level converter2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.

  • 17.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram K.
    Intel Corp., Hillsboro, USA.
    Eckerbert, Daniel
    Chalmers, Göteborg.
    Apperson, Stuart
    Intel Corp., Hillsboro, USA.
    Bloechel, Bradley
    Intel Corp., Hillsboro, USA.
    Borkar, Shekar
    Intel Corp., Hillsboro, USA.
    A 3.5GHz 32mW 150nm multiphase clock generator for high-performande microprocessors.2003In: IEEE International Solid-State Circuits Conference.,2003, Augusta, Maine: J.S.McCarthy Printers , 2003, p. 112-Conference paper (Refereed)
  • 18.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 19.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 20.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Inten Corp., USA.
    Narendra, Siva
    Inten Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 21.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corsp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 22.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Narendra, Siva
    Intel Corp., USA.
    Current leakage reduction for loaded bit-lines in on-chip memory structures2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

  • 23.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A sub-130-nm conditional keeper technique2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, p. 633-638Article in journal (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

  • 24.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp, USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Fast dual-rail dynamic logic style2005Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 25.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Larsson-Edefors, Per
    Chalmers, Göteborg.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Flash (II)-Domino: a fast dual-rail dynamic logic style2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

  • 26.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits1999In: In proceedings of: IEEE International Conference on Electronics, Circuits, And System, 1999, p. 209-212Conference paper (Refereed)
    Abstract [en]

     

  • 27.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering2000In: In proceedings of: IEEE International Symposium on Circuits and Systems. Vol.5, IEEE , 2000, p. 465-468Conference paper (Refereed)
    Abstract [en]

    In this paper, interconnection length estimation is discussed and a general, simple, fast and efficient estimation technique is proposed. In contrast to traditional average length estimation techniques, such as the one based on Rent's rule, the new technique utilizes the topological information of the actual netlist and estimates the length of each interconnection separately. The result of the estimation can be directly used to assign a reasonable R and C to each interconnect, including long and wide buses. Consequently, the new technique enhances the accuracy of power and delay estimations at higher design levels of abstraction

  • 28.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Larsson-Edefors, Per
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits1998In: ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design, 1998, p. 245-249Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a Vdd close to VT and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low Vdd. To avoid reducing Vdd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to VT based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

  • 29.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Manoj, Sinha
    Intel Corp., USA.
    Krishnamurthy, Ram
    Intel Corp., USA.
    Differential charge transfer sense ampliifier2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.

  • 30.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mathew, S.
    Intel Corp., USA.
    Advanced high-performance microprocessor design challenges and solutions2002In: Proceedings of 15th Annual IEEE International ASIC/SOC Conference, 2002, p. 476-476Conference paper (Refereed)
  • 31.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reynaert, Patrick
    Katholieke University of Leuven, Belgium .
    Ytterdal, Trond
    Norwegian University of Science and Technology, Norway .
    Editorial Material: Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC)2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, p. 1511-1514Article in journal (Other academic)
    Abstract [en]

    n/a

  • 32.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Somasekhar, D.
    Intel Corp., Hillsboro, USA.
    Krishnamurthy, Ram
    Intel Corp., Hillsboro, USA.
    De, V.
    Intel Corp., Hillsboro, USA.
    Borkar, S.
    Intel Corp., Hillsboro, USA.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Bitline leakage equalization for sub-100nm caches.2003In: ESSCIRC 2003,2003, Lissabon: Grafica Maiadouro SA , 2003, p. 401-Conference paper (Refereed)
  • 33.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Somasekhar, Dinesh
    Intel Corp., USA.
    Hsu, Steven K.
    Intel Corp., USA.
    Krishnamurthy, Ram K.
    Intel Corp., USA.
    De, Vivek K.
    Intel Corp., USA.
    Statis random access memory with symmetric leakage-compensated bit line.2004Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.

  • 34.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices. Intel Corp., USA.
    Soumyanath, Krishnamurthy
    Intel Corp., USA.
    Krishnamurthy, Ram K.
    Intel Corp., USA.
    Integrated circuits bus architecture including a full-swing, clocked, commongate receiver for fast on-chip signal transmission2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.

  • 35.
    Alvandpour, Atila
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Soumynath, Krishnamurthy
    Intel Corp., USA.
    Krishnamurthy, Ram K.
    Intel Corp., USA.
    Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates.2003Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.

  • 36.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction1997In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1997, p. 305-314Conference paper (Refereed)
    Abstract [en]

    A new wire estimation technique is presented. It utilizes the topology of the netlist and is sensitive to the actual design. It has the unique quality to estimate the length of every power consuming interconnection individually. Compared to other wire length estimation techniques which use average or total wire length, the result of the new technique shows a strong correlation with the result of "real" automatic placement and route tools. Hence it can estimate a reasonable wire capacitance for each interconnection. The individual wire lengths, combined with individual node activities, are essential for an accurate power estimation.

  • 37.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Improving Cell Libraries for Low Power Design1996In: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 1996, p. 317-325Conference paper (Refereed)
  • 38.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Caputa, Peter
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Hansson, Martin
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    TSEK 01, VLSI design projekt 20042003Other (Other (popular science, discussion, etc.))
  • 39.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Carlsson, Ingvar
    EK-ISY Linköpings universitet.
    Natarajan, Sreedhar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A 128Kb 5T SRAM in 0.18mm CMOS.2007In: International Conference on Memory Technology and Design ICMTD 2007,2007, 2007, p. 185-Conference paper (Refereed)
  • 40.
    Asli, Javad Bagheri
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Saberkari, Alireza
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Parallel-Path Amplifier for Fast Output Settling2023In: NEWCAS 2023 CONFERENCE PROCEEDINGS, IEEE, 2023Conference paper (Refereed)
    Abstract [en]

    Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE.

  • 41.
    Azam, Sher
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Jonsson, Rolf
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    High Power, Single Stage SiGaN HEMT Class E Power Amplifier at GHz Frequencies2010In: IEEE International Bhurban Conference on Applied Sciences and Technology, IEEE , 2010Conference paper (Refereed)
  • 42.
    Azam, Sher
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Jonsson, Rolf
    Swedish Defense Research Agency (FOI), Box 1165, SE-581 11 Linkoping, Sweden.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    High Power, Single Stage SiGaN HEMT Class EPower Amplifier at GHz FrequenciesManuscript (preprint) (Other academic)
    Abstract [en]

    A high power single stage class E power amplifier is implemented with lumped elements at 0.89-1.02GHz using Silicon GaN High Electron Mobility Transistor as an active device. The maximum drain efficiency (DE) and power added efficiency (PAE) of 67 and 65 % respectively is obtained with a maximum output power of 42.2 dBm (~ 17 W) and amaximum power gain of 15 dB. We obtained good results at all measured frequencies.

  • 43.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

    Download full text (pdf)
    fulltext
  • 44.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Critical Path Analysis of Two-channel Interleaved Digital MASH ΔΣ Modulators2013In: 2013 NORCHI, 11–12 November, 2013, Vilnius, Lithuania, IEEE , 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

    Download full text (pdf)
    fulltext
  • 45.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, The Institute of Technology.
    Timing challenges in high-speed interleaved ΔΣ DACs2014In: 14th International Symposium on Integrated Circuits (ISIC), 2014, IEEE , 2014, p. 46-49Conference paper (Refereed)
    Abstract [en]

    Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

  • 46.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmailzadeh Najari, Omid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS2013In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

    Download full text (pdf)
    fulltext
  • 47.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ojani, Amin
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs2015In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 7, p. 646-650Article in journal (Refereed)
    Abstract [en]

    Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.

    Download full text (pdf)
    fulltext
  • 48.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    High-Speed On-Chip Interconnect Modeling for Circuit Simulation2004In: Proceedings of the Norchip Conference, Oslo, Norway, November, 2004, p. 143-146Conference paper (Other academic)
  • 49.
    Caputa, Peter
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fredriksson, Henrik
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies2004In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece / [ed] Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou, Springer Berlin/Heidelberg, 2004, Vol. 3254, p. 849-858Conference paper (Refereed)
    Abstract [en]

    In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

  • 50.
    Carlsson, Ingvar
    et al.
    EK. ISY, LiU.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Natarajan, S
    MoSys.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A high density, low leakage, 5T SRAM for embedded caches2004In: ESSCIRC 2004,2004, Leuven: IEEE, Inc. , 2004, p. 215-Conference paper (Refereed)
12345 1 - 50 of 212
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