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  • 1.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Blad, Anton
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy2010In: Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 / [ed] Michael B. Matthews, Washington, DC, USA: IEEE Computer Society , 2010, p. 1168-1172Conference paper (Refereed)
    Abstract [en]

    In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.

  • 2.
    Blad, Anton
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Early-Decision Decoding of LDPC Codes2009Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, withuncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.

    In this thesis, a modification to the sum-product decoding algorithm called early-decision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sum-product decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.

    The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization andenergy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.

  • 3.
    Blad, Anton
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures2011Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, with uncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.

    In this thesis, a modification to the sum-product decoding algorithm called earlydecision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sumproduct decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.

    The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization and energy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.

  • 4.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Axell, Erik
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Larsson, Erik G.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Spectrum Sensing of OFDM Signals in the Presence of CFO: New Algorithms and Empirical Evaluation Using USRP2012In: Proceedings of the 13th IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), IEEE , 2012, p. 159-163Conference paper (Refereed)
    Abstract [en]

    In this work, we consider spectrum sensing of OFDM signals. We deal withthe inevitable problem of a carrier frequency offset, and propose modificationsto some state-of-the-art detectors to cope with that. Moreover, the (modified)detectors are implemented using GNU radio and USRP, and evaluated over aphysical radio channel. Measurements show that all of the evaluated detectorsperform quite well, and the preferred choice of detector depends on thedetection requirements and the radio environment.

  • 5.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Bit-level optimized high-speed architectures for decimation filter applications2008In: IEEE International Symposium on Circuits and Systems,2008, Piscataway, NJ: IEEE , 2008, p. 1914-Conference paper (Refereed)
  • 6.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Energy-Efficient Data Representation in LDPC Decoders2006In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 42, no 18, p. 1051-1052Article in journal (Refereed)
    Abstract [en]

    Data representations for LDPC decoders using the sum-product algorithm in the log-likelihood domain are considered. It is suggested that the look-up table implementation of the domain transform function is separated into two parts, allowing a compact representation of the internal state data. Memories and bus widths can be reduced by typically 16\%, while the imposed hardware overhead is insignificant.

  • 7.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    FPGA implementation of rate-compatible QC-LDPC code decoder2011Conference paper (Other academic)
    Abstract [en]

    The use of rate-compatible error correcting codes offers severaladvantages as compared to the use of fixed-rate codes: a smooth adaptationto the channel conditions, the possibility of incremental Hybrid ARQschemes, as well as simplified code representations in the encoder anddecoder. In this paper, the implementation of a decoder for rate-compatiblequasi-cyclic LDPC codes is considered. The decoder uses check node mergingto increase the convergence speed of the algorithm. Check node mergingallows the decoder to achieve the same performance with a significantlylower number of iterations, thereby increasing the throughput.

    The feasibility of a check node merging decoder is investigated for codesfrom IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the checknode merging algorithm allows the decoder to be implemented using lowerparallelization factors, thereby reducing the logic complexity. The designshave been synthesized to an Altera Cyclone II FPGA, and results showsignificant increases in throughput at high SNR.

  • 8.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures2010In: CIRCUITS SYSTEMS AND SIGNAL PROCESSING, ISSN 0278-081X, Vol. 29, no 1, p. 81-101Article in journal (Refereed)
    Abstract [en]

    Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed finite-length impulse response (FIR) filter structures. In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required. The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90 nm CMOS process.

  • 9.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Redundancy reduction for high-speed FIR filter architectures based on carry-save adder trees2010In: International Symposium on Circuits and Systems, IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.

  • 10.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A Hybrid Early Decision-Probability Propagation Decoding Algorithm for Low-Density Parity-Check Codes2005In: Asilomar Conference on Signals, Systems and Computers,2005, IEEE , 2005, p. 586-Conference paper (Refereed)
    Abstract [en]

    Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate the performance of a hybrid decoding algorithm, using an approximating early decision algorithm and a regular probability propagation algorithm. When the early decision algorithm fails, the block is re-decoded using a probability propagation decoder. As almost all errors are detectable, the error correction performance of the hybrid algorithm is negligibly detoriated. However, simulations still achieve a 32% decrease of memory accesses.

  • 11.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    An early decision decoding algorithm for LDPC codes using dynamic thresholds2005In: European Conference on Circuit Theory and Design,2005, IEEE , 2005, p. III/285-Conference paper (Refereed)
    Abstract [en]

    Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. This reduces the amount of messages passed by the algorithm, which can be expected to reduce the switching activity of a hardware implementation. While direct application of the modification results in severe performance penalties, we show how to adapt the algorithm to reduce the impact, resulting in a negligible decrease in error correction performance.

  • 12.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    An LDPC decoding algorithm utilizing early decisions2005In: National Conference of Radio Science RVK,2005, 2005Conference paper (Refereed)
    Abstract [en]

    We investigate a modification to the sum-product algorithm used for decoding low-density parity-check (LDPC) codes. The sum-product algorithm is algorithmically simple and highly parallelizable, but suffers from high memory usage, making LDPC codes unsuitable for usage in battery powered devices such as cell phones and PDAs. The proposed modification defines a measure of bit reliabilities during the decoding process. Whenever the reliability of a bit is over a certain threshold, the bit is declared decided, and its messages are no longer calculated. We give experimental results for white Gaussian channels, and show that the amount of memory accesses can be substantially reduced, while performance does not suffer significantly. At a bit error rate of 10^-4, the number of memory accesses is halved, while the required transmitter power increases about 0.3 dB.

  • 13.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Early decision decoding methods for low-density parity-check codes2005In: Swedish System-on-Chip Conference,2005, 2005Conference paper (Other academic)
    Abstract [en]

    Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. Currently, there are two early decision schemes proposed. We compare their theoretical performances and their suitability for hardware implementation. We also propose a new decision method, which we call weak decisions, that offers an increase in performance by a factor of two.

  • 14.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering.
    Wanhammar, Lars
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Implementation aspects of an early decision decoder for LDPC codes2005In: NORCHIP Conference,2005, IEEE , 2005, p. 157-Conference paper (Refereed)
    Abstract [en]

    Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we propose an architecture for an early decision decoding algorithm. The algorithm significantly reduces the number of memory accesses. Simulation results show that the increased energy dissipation of the components is small compared to the reduced dissipation of the memories.

  • 15.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Zheng, Meng
    Beijing Institute of Technology, Dept. E. E..
    Fei, Zesong
    Beijing Institute of Technology, Dept. E. E..
    Integer linear programming based optimization of puncturing sequences for quasi-cyclic low-density parity-check codes2010In: Proceedings of International Symposium on Turbo Codes and Iterative Information Processing, IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    An optimization algorithm for the design of puncturing patterns for low-density parity-check codes is proposed. The algorithm is applied to the base matrix of a quasi-cyclic code, and is expanded for each block size used. Thus, storing puncturing patterns specific to each block size is not required. Using the optimization algorithm, the number of 1-step recoverable nodes in the base matrix is maximized. The obtained sequence is then used as a base to obtain longer puncturing sequences by a sequential increase of the allowed recovery delay. The proposed algorithm is compared to one previous greedy algorithm, and shows superior performance for high rates when the heuristics are applied to the base matrix in order to create block size-independent puncturing patterns.

  • 16.
    Blad, Anton
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Zheng, Meng
    Beijing Institute of Technology, Dept. E. E..
    Fei, Zesong
    Beijing Institute of Technology, Dept. E. E..
    Rate-compatible LDPC code decoder using check-node merging2010In: Proceedings of Asilomar Conference on Signals, Systems and Computers, IEEE , 2010, p. 1119-1123Conference paper (Refereed)
    Abstract [en]

    The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as sharing of the encoder and decoder implementations between the codes of different rates. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. Assuming the use of a code ensemble obtained through puncturing of a low-rate mother code, the decoder achieves significantly reduced convergence rates by merging the check node neighbours of the punctured variable nodes. The architecture uses the min-sum algorithm with serial node processing elements to efficiently handle the wide spread of node degrees that results from the merging of the check nodes.

  • 17.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences2006In: Asia Pacific Conference on Circuits and Systems,2006, IEEE , 2006Conference paper (Refereed)
    Abstract [en]

    A formulation based on multirate theory is introduced for analog-to-digital converters using parallel sigma-delta modulators in conjunction with modulation sequences. It is shown how the formulation can be used to analyze a system's sensitivity to channel mismatch errors by means of circulant and pseudo-circulant matrices. It is demonstrated how the time-interleaved-modulated (TIM), Hadamard-modulated (HM) and frequency-band decomposition (FBD) converters can be viewed as special cases of this more general description, and it is shown why the TIM and HM ADCs are sensitive to channel mismatch errors, whereas the FBD ADCs are not.

  • 18.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Multirate formulation for mismatch sensitivity analysis of analog-to-digital converters that utilize parallel S?-modulators2008In: Eurasip Journal on Advances in Signal Processing, ISSN 1687-6172, Vol. 2008Article in journal (Refereed)
    Abstract [en]

    A general formulation based on multirate filterbanktheory for analog-to-digital converters using parallel sigmadeltamodulators in conjunction with modulation sequences ispresented. The time-interleaved modulators (TIMs), Hadamard modulators(HMs), and frequency-band decomposition modulators(FBDMs) can be viewed as special cases of the proposeddescription. The usefulness of the formulation stems from itsability to analyze a system's sensitivity to aliasing due to channel mismatch and modulation sequence level errors. BothNyquist-rate and oversampled systems are considered, and it isshown how the matching requirements between channels canbe reduced for oversampled systems. The new formulation isuseful also for the derivation of new modulation schemes, andan example is given of how it can be used in this context.

  • 19.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Design Trade-Offs for Linear-Phase FIR Decimation Filters and SD-Modulat ors2006In: 14th European Signal Processing Conference,2006, Wien, Austria: EURASIP , 2006Conference paper (Refereed)
    Abstract [en]

    In this paper we examine the relation between signal-to-noise-ratio, oversampling ratio, transition bandwidth, and filter order for some commonly used sigma-delta-modulators and corresponding decimation filters. The decimation filters are equi-ripple finite impulse response filters and it is demonstrated that, for any given filter order, there exists an optimum choice of the stopband ripple and stopband edge which minimizes the signal-to-noise-ratio degradation.

  • 20.
    Blad, Anton
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Johansson, Håkan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    An RF sampling radio frontend based on sigmadelta-conversion.2006In: 24th Norchip Conference,2006, IEEE , 2006, p. 133-136Conference paper (Refereed)
  • 21.
    Cipriano, Antonio
    et al.
    Thales Communications and Security, Colombes, France.
    Agostini, Philippe
    Thales Communications and Security, Colombes, France.
    Blad, Anton
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, The Institute of Technology.
    Knopp, Raymond
    Institut Eurecom, Sophia Antipolis, France.
    Cooperative Communications with HARQ in a Wireless Mesh Network Based on 3GPP LTE2012In: Signal Processing Conference (EUSIPCO), 2012, IEEE , 2012, p. 1004-1008Conference paper (Refereed)
    Abstract [en]

    This paper presents some results from of the FP7 ICT-LOLA (achieving LOw LAtency in wireless communications) project on the design of clusterized wireless mesh network based on 3GPP LTE. First, we focus on the general MAC/PHY structure of the clusterized mesh network based on 3GPP LTE. Then, the concept of virtual link is presented for inter-cluster communications combining MAC layer forwarding, hybrid automatic repeat request (HARQ) and cooperative communications with Decode and Forward (DF). The goal of a virtual link is to enable low latency data transfer in inter-cluster communications. The virtual link solution is studied by simulations thanks to OpenAirInterface which integrates LTE MAC and PHY layer procedures, as well as adaptations needed for the LOLA wireless mesh network. Simulation results show that the proposed distributed solution smoothly adapts to the link conditions. A loss in throughput efficiency is the price to be paid in certain configurations for the distributed operation of the virtual link. Nevertheless, the technique helps in reducing the average number of transmissions thus contributing to improve the latency of the system.

  • 22.
    Zheng, Meng
    et al.
    Beijing Institute of Technology, Dept. E. E..
    Fei, Zesong
    Beijing Institute of Technology, Dept. E. E..
    Chen, Xiang
    Beijing Institute of Technology, Dept. E. E..
    Kuang, Jingming
    Beijing Institute of Technology, Dept. E. E..
    Blad, Anton
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Power Efficient Partial Repeated Cooperation Scheme with Regular LDPC Code2010In: Proceedings of Vehicular Technology Conference, Spring, IEEE , 2010Conference paper (Refereed)
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