liu.seSearch for publications in DiVA
Change search
Refine search result
123 1 - 50 of 113
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Adolfsson, Dan
    et al.
    NXP Semiconductors corp., Eindhoven, the Netherlands.
    Siew, Joanna
    Philips Applied Technologies, Eindhoven, the Netherlands.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Marinissen, Erik Jan
    IMEC, Leuven, Belgium).
    Deterministic Scan-Chain Diagnosis for Intermittent Faults2009In: European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009 (Poster)., 2009Conference paper (Other academic)
  • 2.
    Adolfsson, Dan
    et al.
    NXP Semiconductors corp., Eindhoven, the Netherlands.
    Siew, Joanna
    Philips Applied Technologies, Eindhoven, the Netherlands.
    Marinissen, Erik Jan
    IMEC, Leuven, Belgium.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    On Scan Chain Diagnosis for Intermittent Faults2009In: IEEE Asian Test Symposium (ATS), Taichung, Taiwan, November 23-26, 2009., 2009, p. 47-54Conference paper (Refereed)
    Abstract [en]

    Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

  • 3.
    Bäckström, David
    et al.
    IDA Linköpings Universitet.
    Carlsson, Gunnar
    Digital Processing Platform Ericsson AB.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Boundary-Scan Test Control in the ATCA Standard2005In: EEE European Board Test Workshop,2005, 2005Conference paper (Other academic)
    Abstract [en]

    The backplane in a multi-board system has a limited wiring capability, which makes additional backplane Boundary-Scan wiring to link the boards highly costly. The problem is to access the Boundary-Scan tested boards with the Boundary- Scan controller at the central board. In this paper we propose an approach suitable for the Advanced Telecom Computing Architecture standard where we make use of the existing I2C-bus and the Intelligent Platform Management Bus (IPMB) protocol for application of operational tests. We have defined a protocol with commands and responses as well as a test data format for storing test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed a demonstrator.

  • 4.
    Bäckström, David
    et al.
    Dept. Computer and Information Science Linköpings Universitet.
    Carlsson, Gunnar
    Digital Processing Platform Ericsson AB.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Remote Boundary-Scan System Test Control for the ATCA Standard2005In: International Test Conference ITC05,2005, Austin, Texas, USA: IEEE Computer Society Press , 2005, p. 32.2-Conference paper (Refereed)
    Abstract [en]

    The backplane in a multi-board system has a limited wiring capability, which makes additional backplane Boundary-Scan wiring to link the boards highly costly. The problem is to access the Boundary-Scan tested boards with the Boundary- Scan controller at the central board. In this paper we propose an approach suitable for the Advanced Telecom Computing Architecture standard where we make use of the existing I2C-bus and the Intelligent Platform Management Bus (IPMB) protocol for application of operational tests. We have defined a protocol with commands and responses as well as a test data format for storing test data on the boards to support the remote execution of Boundary-Scan tests. For validation of the proposed approach we have developed a demonstrator.

  • 5.
    Carlsson, Gunnar
    et al.
    Ericsson AB, Stockholm, Sweden.
    Holmqvist, Johan
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Protocol requirements in an SJTAG/IJTAG environment2007In: IEEE International Test Conference, 2007, IEEE , 2007, p. 942-950Conference paper (Refereed)
    Abstract [en]

    Integrated Circuits, Printed Circuits Boards, and Multi-board systems are becoming increasingly complex to test. A major obstacle is test access, which would be eased by effective standards for the communication between devices-under-test (DUTs) and the test manager. Currently, the Internal Joint Test Access Group (IJTAG) work at micro-level on a standard for interfacing embedded on-chip instruments while the System JTAG (SJTAG) work at macro-level on a standard for system-level test management that connects IJTAG compatible instruments with the system test manager. In this paper we discuss requirements on a test protocol to be used in an SJTAG/IJTAG environment. We have from a number of use scenarios made an analysis and defined protocol requirements. We have taken the Standard Test and Programming Language (STAPL), which is built around a player (interpreter), and defined required extensions. The extensions have been implemented in an extended version of STAPL and we have made experiments with a PC acting as test controller and an FPGA being the DUT.

  • 6.
    Carlsson, Gunnar
    et al.
    Ericsson, Linköping, Sweden.
    Jutman, Artur
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    SoC-Level Fault Management based on P1687 IJTAG2011Other (Other academic)
    Abstract [en]

    Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The presentation describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard allows to create an efficient and regular network for handling fault detection information, manage test and system resources as a system-wide background process during system operation.

  • 7.
    Dubois, Tobias
    et al.
    Philips Research Labs.
    Azimane, Mohamed
    Philips Research Labs.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Marinissen, Erik Jan
    Philips Research Labs.
    Wielage, Paul
    Philips Research Labs.
    Wouters, Clemens
    Philips Semiconductors.
    High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO2006In: 14th Philips Research IC Test Seminar,2006, 2006Conference paper (Other academic)
  • 8.
    Dubois, Tobias
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Marinissen, Erik Jan
    NXP Semiconductors Research, The Netherlands.
    Azimane, Mohamed
    NXP Semiconductors Research, The Netherlands.
    Wielage, Paul
    NXP Semiconductors Research, The Netherlands.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Wouters, Clemens
    Digital Library Technology NXP Semiconductors, The Netherlands.
    Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO2007In: Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, Nice, France: IEEE , 2007, p. 859-864Conference paper (Refereed)
    Abstract [en]

    Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clocks, which is at least a factor two smaller and also faster than SRAM-based and standard-cell-based counterparts. The detection qualities of the FIFO test for both hard and weak resistive shorts and opens have been analyzed by an IFA-like method based on analog simulation. The defect coverage of the initial FIFO test for shorts in the bit-cell matrix has been improved by inclusion of an additional data background and low-voltage testing; for low-resistant shorts, 100% defect coverage is obtained. The defect coverage for opens has been improved by a new test procedure which includes waiting periods.

  • 9.
    Edbom, Stina
    et al.
    IDA Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint2004In: 2004 IEEE Asian Test Symposium ATS 2004,2004, Kenting, Taiwan: IEEE Computer Society Press , 2004, p. 254-Conference paper (Refereed)
    Abstract [en]

    The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE's (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.

  • 10. Holmqvist, Johan
    et al.
    Carlsson, Gunnar
    Digital Processing Platform Ericsson AB, Sweden.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Extended STAPL as SJTAG Engine2007In: IEEE European Test Symposium,2007, Freiburg, Germany: IEEE Computer Society Press , 2007, p. 119-Conference paper (Refereed)
    Abstract [en]

    Integrated Circuits (ICs) and multi-board systems are becoming increasingly complex to test. A key to successful testing is effective standards. Currently, at micro level the Internal JTAG (IJTAG) focuses on the development of a standard for embedded on-chip instruments while at macro level the System JTAG (SJTAG) works on defining a standard for system level test management; mainly connecting the IJTAG standard with the system test manager. In this paper we discuss language requirement for making and handling access between the test manager and embedded instruments. As a base-line we make use of the Standard Test and Programming Language (STAPL). We have identified a number of required extensions that we have implemented in an extended STAPL++ player (interpreter) and language. We have performed initial experiments where we simulated an embedded environment with a PC as test controller running the new player and an FPGA serving as device-under-test.

  • 11.
    Ingelsson, Urban
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chang, Shih-Yen
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Faculty of Educational Sciences.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Measurement Point Selection for In-Operation Wear-Out Monitoring2011In: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011., IEEE , 2011, p. 381-386Conference paper (Refereed)
    Abstract [en]

    In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wearout monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

  • 12.
    Ingelsson, Urban
    et al.
    IDA Linköpings Universitet.
    Goel, Sandeep Kumar
    IC Design Digital Design and Test Philips Research Labs.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Marinissen, Erik Jan
    IC Design Digital Design and Test Philips Research Labs.
    Test Scheduling for Modular SOCs in an Abort-on-Fail Environment2005In: IEEE European Test Symposium ETS 05,2005, Tallinn, Estonia: IEEE Computer Society Press , 2005Conference paper (Refereed)
    Abstract [en]

    Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module s manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC 02 SOC Test Benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction in the expected test application time, without any modification to the SOC or ATE.

  • 13.
    Larsson, Anders
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chakrabarty, Krishnendu
    Duke University, USA.
    Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs2010In: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010Chapter in book (Other academic)
    Abstract [en]

    Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

    Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.

  • 14.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Electrical and Computer Engineering Dept. Duke University, USA.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns2008In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, p. 188-Conference paper (Refereed)
    Abstract [en]

    The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.

  • 15.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing2007In: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,2007, Krakow, Poland: IEEE Computer Society Press , 2007, p. 61-Conference paper (Refereed)
    Abstract [en]

    The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipment (ATE) memory. Test compression and test sharing have been proposed to reduce the test data volume, while test infrastructure and concurrent test scheduling have been developed to reduce the test application time. In this work we propose an integrated test scheduling and test infrastructure design approach that utilizes both test compression and test sharing as basic mechanisms to reduce test data volumes. In particular, we have developed a heuristic to minimize the test application time, considering different alternatives of test compression and sharing, without violating a given ATE memory constraint. The results from the proposed Tabu Search based heuristic have been validated using benchmark designs and are compared with optimal solutions.

  • 16.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Technique for Optimization of System-on-Chip Test Data Transportation2004In: 9th IEEE European Test Symposium,2004, 2004, p. 179-180Conference paper (Refereed)
    Abstract [en]

    We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.

  • 17.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip2003In: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03,2003, Cambridge, MA, USA: IEEE Computer Society Press , 2003, p. 385-Conference paper (Refereed)
    Abstract [en]

    Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs.

  • 18.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip2005In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, p. 403-Conference paper (Refereed)
    Abstract [en]

    The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM will shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.

  • 19.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimized Integration of Test Compression and Sharing for SOC Testing2007In: Design, Automation, and Test in Europe Conference DATE07,2007, Nice, France: IEEE Computer Society Press , 2007, p. 207-Conference paper (Refereed)
    Abstract [en]

    The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.

  • 20.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    SOC Test Scheduling with Test Set Sharing and Broadcasting2005In: IEEE Asian Test Symposium,2005, Kolkata, India: IEEE Computer Society Press , 2005, p. 162-Conference paper (Refereed)
    Abstract [en]

    Due to the increasing test data volume needed to test core-based System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.

  • 21.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Zhang, Xin
    Masters Programme in Computer Science Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Dept. of Electrical and Computer Engineering Duke University, USA.
    Core-Level Expansion of Compressed Test Patterns2008In: Proceedings of the Asian Test Symposium, Sapporo, JAPAN: IEEE Computer Society , 2008, p. 277-282Conference paper (Refereed)
    Abstract [en]

     The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.

  • 22.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Zhang, Xin
    Masters Programme in Computer Science Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Dept. of Electrical and Computer Engineering Duke University, USA.
    SOC Test Optimization with Compression-Technique Selection2008In: Proceedings - International Test Conference, IEEE , 2008, p. 1-Conference paper (Other academic)
    Abstract [en]

    The increasing test-data volumes needed for the testing of system-on-chip (SOC) lead to long test times and high memory requirements. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. Therefore, we propose a technique where compression-technique selection is integrated with core wrapper design, test architecture design, and test scheduling to minimize the SOC test time and the test-data volume.

  • 23.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment2008In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, no 4, p. 275-284Article in journal (Refereed)
    Abstract [en]

     The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed. Further, the proposed architecture efficiently tackles low throughput as the architecture allows multi-site testing at a constant ATE memory requirement, which is independent of the number of tested ICs. Advantages of the architecture, compared with test compression architecture, are that diagnostic capabilities are not reduced and there is no need for special handling of unknowns (X) in the produced test responses (PR). Experiments on ISCAS benchmark circuits and an industrial circuit have been performed.

  • 24.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    An Integrated System-Level Design for Testability Methodology2000Doctoral thesis, monograph (Other academic)
    Abstract [en]

    HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems.

    The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design.

    The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources.

    Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system.

    Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.

  • 25.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Combined Test Data Compression and Abort-on-Fail Test2006In: 24th IEEE Norchip Conference,2006, Linköping: IEEE Computer Society Press , 2006Conference paper (Refereed)
    Abstract [en]

    The increasing test data volume needed for the testing of System-on-Chips (SOCs) leads to high Automatic Test Equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of Multiple Input Signature Response Analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as patternbased abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs.

  • 26.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Conference Reports - RASDAT 2011: Workshop on Reliability Aware System Design and Test2011In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 28, no 3, p. S. 82-83p. 82-83Article in journal (Other academic)
    Abstract [en]

    Conference Reports features the second IEEE International Workshop on Reliability Aware System Design and Test (RASDAT),which was held in conjunction with the 24th International Conference on VLSI Design.

  • 27.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Conference Reports: ETS 2011: European Test Symposium2011In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 28, no 5, p. 95-95Article in journal (Other (popular science, discussion, etc.))
  • 28.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Core Selection Integrated in the SOC Test Solution Design-Flow2004Other (Other (popular science, discussion, etc.))
  • 29.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Integrating Core Selection in the SOC Test Solution Design-Flow2004In: International Test conference ITC04,2004, Charlotte, NC, USA: IEEE Computer Society Press , 2004, p. 1349-Conference paper (Refereed)
    Abstract [en]

    We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

  • 30.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Introduction to Advanced System-on-Chip Test Design and Optimization2005Book (Other academic)
    Abstract [en]

    Testing of Integrated Circuits is important to ensure the production of fault-free chips. However, testing is becoming cumbersome and expensive due to the increasing complexity of these ICs. Technology development has made it possible to produce chips where a complete system, with an enormous transistor count, operating at a high clock frequency, is placed on a single die - SOC (System-on-Chip). The device size miniaturization leads to new fault types, the increasing clock frequencies enforces testing for timing faults, and the increasing transistor count results in a higher number of possible fault sites. Testing must handle all these new challenges in an efficient manner having a global system perspective. Test design is applied to make a system testable. In a modular core-based environment where blocks of reusable logic, the so called cores, are integrated to a system, test design for each core include: test method selection, test data (stimuli and responses) generation (ATPG), definition of test data storage and partitioning [off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST (Built-In Self-Test)], wrapper selection and design (IEEE std 1500), TAM (test access mechanism) design, and test scheduling minimizing a cost function whilst considering limitations and constraint. A system test design perspective that takes all the issues above into account is required in order to develop a globally optimized solution. SOC test design and its optimization is the topic of this book. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.

  • 31.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Preemptive system-on-chip test scheduling2004In: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E87D, no 3, p. 620-629Article in journal (Refereed)
    Abstract [en]

    In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

  • 32.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Amirijoo, Mehdi
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory.
    Karlsson, Daniel
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    What Impacts Course Evaluation?2007In: 12th SIGCSE Conf. on Innovation and Technology in Computer Science Education,2007, 2007, p. 333-333Conference paper (Refereed)
    Abstract [en]

    Today most universities are using course evaluations. However, course evaluations are often discussed and questioned. This paper reports on a survey where we aim at finding out (1) if students have a preconceived notion of a course, (2) if course evaluation scores can be predicted early in a course, (3) if exam throughput impacts course evaluation, and (4) if web-based evaluation reflects the general opinion from students. The results from the study indicate that students do not let preconceived notion impact nor does exam throughput matter to course evaluation. Further, the final web-based results seem to correlate with opinion of students attending lectures. However, the evaluation grades tend to be defined early in the course; hence first impression lasts.

  • 33.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Arvidsson, Klas
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science.
    Fujiwara, H
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Efficient test solutions for core-based designs2004In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 23, no 5, p. 758-775Article in journal (Refereed)
    Abstract [en]

    A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost.

  • 34.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Arvidsson, Klas
    Embedded Systems Lab. Linköpings Universitet.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Integrated Test Scheduling, Test Parallelization and TAM Design2002In: IEEE Asian Test Symposium ATS02,2002, Tamuning, Guam, USA: IEEE Computer Society Press , 2002, p. 397-Conference paper (Refereed)
    Abstract [en]

    We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.

  • 35.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Edbom, Stina
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint2007In: Vlsi-Soc: From Systems To Silicon / [ed] Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer, Boston, USA: Springer , 2007, p. 221-244Chapter in book (Other academic)
    Abstract [en]

    Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

  • 36.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Edbom, Stina
    Dept. Computer and Information Science Linköpings Universitet.
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint2005In: IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005},2005, 2005, p. 429-434Conference paper (Refereed)
    Abstract [en]

    The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automatic Test Equipment) memory. In this paper, we (1) define a test quality metric based on fault coverage, defect probability and number of applied test vectors, and (2) a test data truncation scheme. The truncation scheme combines (1) test data (vector) selection for each core based on our metric, and (2) scheduling of the execution of the selected test data, in such a way that the system test quality is maximized, while the selected test data is guaranteed to fit the ATEs memory. We have implemented the technique and the experimental results, produced at reasonable CPU times, on several ITC02 benchmarks show that high test quality can be achieved by a careful selection of test data.

  • 37.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Edbom, Stina
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint2007In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 1, no 1, p. 27-37Article in journal (Refereed)
    Abstract [en]

    Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

  • 38.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, H
    System-on-chip test scheduling with reconfigurable core wrappers2006In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 14, no 3, p. 305-309Article in journal (Refereed)
    Abstract [en]

    The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n), n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection testsre and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound.

  • 39.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Optimal System-on-Chip Test Scheduling2003In: 12th IEEE Asian Test Symposium ATS03,2003, Xian, China: IEEE Computer Society Press , 2003, p. 306-Conference paper (Refereed)
    Abstract [en]

    In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

  • 40.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers2002Other (Other (popular science, discussion, etc.))
    Abstract [en]

    In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equal to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm producing an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations and also the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

  • 41.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Power Constrained Preemptive TAM Scheduling2002In: 7th IEEE European Test Workshop,2002, Corfu, Greece: IEEE Computer Society Press , 2002, p. 119-Conference paper (Refereed)
    Abstract [en]

    We integrate scan-chain partitioning and preemptive test access mechanism (TAM) scheduling for core-based systems under power constraint. We also outline a flexible power conscious test wrapper to increase the flexibility in the scheduling process by (1) allowing several different bandwidths at cores and (2) controlling the cores test power consumption, which makes it possible to increase the test clock. We model the scheduling problem as a Bin-packing problem and we discuss the transformations: (1) TAM-time and (2) power-time and the possibilities to achieve an optimal solution and the limitations. We have implemented our proposed preemptive TAM scheduling algorithm and through experiments we demonstrate its efficiency.

  • 42.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Test Resource Partitioning and Optimization for SOC Designs2003In: 2003 IEEE VLSI Test Symposium VTS03,2003, Napa Valley, USA: IEEE Computer Society Press , 2003, p. 319-Conference paper (Refereed)
    Abstract [en]

    We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.

  • 43.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Gilani, Irtiyaz
    Dept. Information and Computer Science Linköpings Universitet.
    A Test Data Compression Architecture with Abort-on Fail Capability2005In: IEEE Workshop on RTL and High Level Testing WRTLT,2005, 2005Conference paper (Other academic)
  • 44.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Student-oriented Examination in a Computer Architecture Course2004In: 9th Annual Conference on Innovation and Technology in Computer Science Education,2004, 2004, p. 245-245Conference paper (Refereed)
    Abstract [en]

    Learning is a highly individual process. Some prefer learning by reading the course material, others learn best by listening to a lecture, while some like to learn in a trial-and-error way by themselves in a laboratory assignment. A good learning scheme is individual. A scheme that is good for some persons might not at all be good scheme for someone else. It is important to understand your own personal way to learn, but also when organizing a course individual learning alternatives should be acknowledged. Examination in a course can be seen as a test occasion or as a learning occasion. Traditionally, examination has been an occasion where knowledge is tested. Written exams can be used to test the theory and laboratory work to test practical aspects of the course material. For laboratory work the distinction between learning and test of learning is somewhat unclear. The learning and the test of learning are mixed. However, in general, examination can be seen as an occasion to learn and/or to test knowledge. We have, in a Computer Architecture course, taken the view that (1) learning is an individual process, and (2) that examination is a learning occasion. The consequence of our view (1)+(2) is basically that examination should be individual, or student-oriented. Alternatives to traditional examination is also supported when taking gender, cultural, and age perspectives. We therefore developed two examination tracks where the students in the beginning of the course decided what track to follow. Common for both tracks is that credits are given that can be counted for in the written exam

  • 45.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling2008In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 24, no 5, p. 497-504Article in journal (Refereed)
    Abstract [en]

    The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach. © 2008 Springer Science+Business Media, LLC.

  • 46.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling2003In: International Test Conference ITC 2003,2003, Charlotte, NC, USA: IEEE , 2003, p. 1135-Conference paper (Refereed)
    Abstract [en]

    This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage with the proposed wrapper is that at each core it allows (1) a exible TAM (test access mechanism) bandwidths, and (2) a possibility to select the appropriate test power consumption. Our scheduling technique, an extension of a preemptive scheduling approach,produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. Experimental results show the efficiency of our approach.

  • 47.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Technique for Test Infrastructure Design and Test Scheduling2000In: Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS 2000,2000, Smolenice Castle, Slovakia: IEEE Computer Society Press , 2000, p. 26-Conference paper (Refereed)
    Abstract [en]

    We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.

  • 48.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated Framework for the Design and Optimization of SOC Test Solutions2002In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 18, no 4-5, p. 385-400Article in journal (Refereed)
    Abstract [en]

    We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.

  • 49.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated Framework for the Design and Optimization of SOC Test Solutions2002In: SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. / [ed] Krishnendu Chakrabarty, Boston, USA: Kluwer Academic Publishers , 2002, p. 21-36Chapter in book (Other academic)
    Abstract [en]

    We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.

  • 50.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated System-on-Chip Test Framework2008In: Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Dordrecht, The Netherlands: Springer , 2008, 1, p. 439-454Chapter in book (Other academic)
    Abstract [en]

    In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

123 1 - 50 of 113
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf