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  • 1.
    Andersson, Niklas
    et al.
    Ericsson Microelectronics AB.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Models and Implementation of a Dynamic Element Matching DAC2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, p. 7-16Article in journal (Refereed)
    Abstract [en]

    The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been suggested as a promising method to improve matching between the DAC''s reference levels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process. The measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable performance.

  • 2.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling and Implementation of Current-Steering Digital-to-Analog Converters2005Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications.

    Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work.

    Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source.

    The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations.

    It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given.

    Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

  • 3.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-Bit dual current-steering DAC2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003Conference paper (Other academic)
    Abstract [en]

    A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.

  • 4.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A differential DAC architecture with variable common-mode level2002In: Proc. 2002 IEEE Int. Symp. on Circuits and Systems, ISCAS'02, 2002, p. I-113-I-116Conference paper (Refereed)
    Abstract [en]

    A differential current-steering digital-to-analog converter (DAC) architecture allowing the common-mode level of the input signal to be varied is presented. Simulation results with models of different DAC nonlinearities indicate that the proposed architecture has a potential of improving the linearity of the converters.

  • 5.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A method of segmenting digital-to-analog converters2003In: Proc. IEEE Southwest Symposium on Mixed-Signal Design, SSMSD'03, 2003, p. 32-37Conference paper (Refereed)
    Abstract [en]

    Segmented architectures are often used in digital-to-analog converters (DACs). Here we propose a DAC structure based on recursive decomposition of an N-bit binary DAC into two (N-1) bit DACs and one 1 bit DAC. A DAC model that includes matching errors has been simulated. The simulation results indicate that by using four layers of decomposition it is possible to achieve similar performance as when using seven bits of traditional segmentation.

  • 6.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Combining DACs for improved performance2002In: Proc. 4th IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and their Applications, ADDA'02, 2002Conference paper (Refereed)
    Abstract [en]

    This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.

  • 7.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Spectral shaping of DAC nonlinearity errors through modulation of expected errors2001In: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, IEEE , 2001, Vol. 3, p. 417-420Conference paper (Refereed)
    Abstract [en]

    Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included

  • 8.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A parameterized cell-based design approach for digital-to-analog converters2004In: Proc. IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, p. 225-228Conference paper (Refereed)
    Abstract [en]

    Due to the lack of proper design automation tools, designers are often forced to use full-custom design methodologies when designing analog and mixed-signal circuits. In this work, we discuss a design methodology based on parameterized cells intended for efficient design. The methodology is illustrated with the design of a 12-bit configurable current-steering DAC. Because the cells are parameterized, their layout must be described in a generalized way, resulting in a longer design time compared with a manual layout of a fixed circuit. However, the parameterized approach simplifies iteration of the layout process and block reuse.

  • 9.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering.
    A testbed for different codes in digital-to-analog converters2004In: Proc. Swedish System-on-Chip Conf. 2004, SSoCC'04, 2004Conference paper (Other academic)
  • 10.
    Andersson, Ola
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A yield-enhancement strategy for binary-weighted DACs2005In: Proc. European Conf. Circuit Theory and Design 2005, ECCTD'05, 2005, , p. 55-58p. 55-58Conference paper (Refereed)
    Abstract [en]

    One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.

  • 11.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Dynamic element matching in decomposed digital-to-analog converters2004In: Proc. IEEE NORCHIP'04, Denmark: TechnoData A/S , 2004, , p. 187-190p. 187-190Conference paper (Refereed)
    Abstract [en]

    A dynamic element matching (DEM) technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed converter architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90% yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.

  • 12.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Partial decomposition of digital-to-analog converters2004In: Proc. 12th IEEE Mediterranean Electrotechnical Conf., MELECON'04, 2004, p. 193-196Conference paper (Refereed)
    Abstract [en]

    The decomposed DAC architecture was recently proposed as an alternative to the traditional segmented architecture. In this work, we present a modified version of the decomposed architecture with reduced hardware complexity denoted the partially decomposed architecture. Behavioral-level simulations indicate that the partially decomposed architecture is a good alternative for signals with Gaussian distribution, whereas the original decomposed or segmented architectures are preferred for sinusoidal signals.

  • 13.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Characterization of a CMOS current-steering DAC using state-space models2000In: Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, IEEE , 2000, Vol. 2, p. 668-671 vol.2Conference paper (Refereed)
    Abstract [en]

    Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters

  • 14.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs1999In: Proceedings of the 17th Norchip Conference, 1999Conference paper (Other academic)
    Abstract [en]

    In analog and mixed-mode circuits the matching between circuit elements is crucial.For example, in binary encoded digital-to-analog converters (DACs) the matchingbetween different bit weights can set the limit on the performance. Related to earlier workmodeling the influence of stochastic matching, the influence of graded element matching errorson the performance of current-steering DACs is shown. Presented are calculated results thatcorrelate very well with simulated results. As performance measures we use both static measuresas DNL and INL as well as frequency domain parameters as SNDR and SFDR. This discussioncan also be applied to other DAC structures, for example switched-capacitor.

  • 15.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A dynamic element matching technique for flash analog-to-digital converters2004In: Proc. 8th Nordic Signal Processing Symp., NORSIG'04, 2004, p. 137-140Conference paper (Refereed)
    Abstract [en]

    A flash analog-to-digital converter is proposed that employs a new dynamic element matching architecture. The architecture uses a new strategy of incorporating switches in the voltage reference generator that allows lower hardware complexity and higher conversion speed than comparable converters. The converter has been modeled and simulated on a behavioral level in Matlab. The results indicate good linearity properties that together with the expected speed performance should make it suitable in intended communications applications.

  • 16.
    Säll, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering.
    A study of digital decoders in flash analog-to-digital converters2004In: Proc. IEEE Int. Symp. Circuits Syst., ISCAS'04, 2004, p. I-129-I-132Conference paper (Refereed)
  • 17.
    Vesterbacka, Mark
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Ola
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Niklas
    n/a.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Using different weights in DACs2002In: Proc. 4th IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and their Applications, ADDA'02, 2002Conference paper (Refereed)
    Abstract [en]

    In this paper we discuss some properties of different codes with their respective sets of weights to be used in digital-to-analog converters (DACs). The thermometer (unratioed) code is widely used instead of a binary code in the most significant bits of a segmented DAC to reduce errors due to weight and timing mismatch. The binary and thermometer codes are two extremes, where the first offers a small digital hardware cost and the latter a large cost. We have investigated some of the properties of these codes and codes with properties in-between; such as linear, polynomial, and segmented codes. Some new ideas and results on using different sets of weights and how to generate them are presented. We present simulation results for some low-order polynomial codes.

1 - 17 of 17
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