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  • 1.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Two-tone PLL for on-chip IP3 test2010In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, p. 3549-3552Conference paper (Refereed)
    Abstract [en]

    This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

  • 2.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Two-Tone PLL for on-Chip IP3 Test2010In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
  • 3.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ADC on-Chip Dynamic Test by PWM Technique2008In: International Conference on Signals and Electronic Systems, IEEE , 2008, p. 15-18Conference paper (Refereed)
    Abstract [en]

    This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

  • 4.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator2010In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, p. 393-396Conference paper (Refereed)
    Abstract [en]

    This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

  • 5.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of Two-Tone RFGenerator for On-Chip IP3/IP2 TestManuscript (preprint) (Other academic)
  • 6.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    On-Chip Spectral Test for High-Speed ADCs by ΣΔ Technique2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 661-664Conference paper (Refereed)
    Abstract [en]

    Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance spectral measurements a frequency plan is used taking into account the type of ΣΔ modulation (low-pass and band-pass) including the FFT processing gain. Higher order modulation schemes are avoided to manage the ΣΔ quantization noise without resorting to a more complicated filter. For spectral measurements up to the Nyquist frequency, we propose a dedicated low-pass/band-pass ΣΔ modulation scheme that limits spreading of the low-frequency quantization noise by ADC under test that tends to obstruct the test measurements at high frequencies. Correction technique for NRTZ encoding suitable for ADCs with very high clock frequencies is put in perspective. The presented technique is illustrated by simulation examples of a Nyquist-rate ADC under test.

  • 7.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique2009In: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey, IEEE , 2009, p. 105-108Conference paper (Refereed)
    Abstract [en]

    This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.

  • 8.
    Ahmad, Shakeel
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test2010In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic)
  • 9.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Self-Tuning Technique for Optimization of Dual Band LNA2008In: European Wireless Technology Conference (EuWiT), EuMW 2008, October 27-28, 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 178-181Conference paper (Refereed)
    Abstract [en]

    This paper presents a self-tuning technique for optimization of a dual band LNAthat can be used in a flexible RF front-end suitable for IEEE 802.11a/b/g WLANapplications. With this tuning technique the LNA can perform self-calibrationfor the optimal performance. A possible shift in resonance frequency due toprocess and temperature variations can be compensated by this method. Theproposed self-tuning technique is implemented by using a simple RF detector atthe LNA output. Based on the DC value provided by this detector the LNA istuned for a maximum gain through the tuning loop, which incorporates ADC,digital base-band and DAC. We show that the tuning error can be within halfLSB of ADC provided the DAC and ADC resolutions are constraint by aspecified condition. For 4-bit case this value corresponds to a gain error of0.4 dB. The LNA has been implemented in 0.2μm GaAs process offered byOMMICTM. In measurements the LNA achieves a gain of 15.1 dB and 21.6 dBin the upper and lower band, respectively, with corresponding NF of 3.8 dB and2.8 dB. In the lower band the measured IIP3 is -3 dBm and 1dB_CP is -8 dBm.

  • 10.
    Ahsan, Naveed
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Ouacha, Aziz
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A tunable LNA for flexible RF front-end.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 11.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dual Band Tunable LNA for Flexible RF Front End2007In: Proceedings of the IEEE International Bhurban Conference on Applied Sciences & Technology (IBCAST 2007), January 8-11, 2007, Islamabad, Pakistan, IEEE Explore , 2007, p. 19-22Conference paper (Refereed)
    Abstract [en]

    This paper presents a dual band LNA that can be switched between two bands (2.4 GHz & 5.2 GHz) for IEEE 802.1 la/b/g WLAN applications. The LNA is also tunable within each band and the tuning is incorporated by on-chip varactors. The test chip consists of two fully integrated narrow-band tunable LNAs along with SPDT switch. For power saving one LNA can be switched off. The technology process is 0.2 mum GaAs offered by OMMIC. The LNA can achieve a relatively good performance over the two bands as demonstrated by simulation. With a 3V supply, the LNA has a gain of 26.2 dB at 2.4 GHz and 21.8 dB at 5.2 GHz and the corresponding NF varies between 2.07 dB and 1.84 dB, respectively. The LNA has an IIP3 of -7 dBm at 2.4 GHz and -1.6 dBm at 5.2 GHz.

  • 12.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic)
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

  • 13.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Highly Linear Wideband Low Power Current Mode LNA2008In: Proceedings from the ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, IEEE , 2008, p. 73-76Conference paper (Refereed)
    Abstract [en]

    This paper presents design considerations for low power, highly linear currentmode LNAs that can be used for wideband RF front-ends for multistandardapplications. The circuit level simulations of the proposed architecture indicatethat with optimal biasing a high value of IIP3 can be obtained. A comparison ofthree scenarios for optimal bias is presented. Simulation results indicate thatwith the proposed architecture, LNAs may achieve a maximum NF of 3.6 dBwith a 3 dB bandwidth larger than 10 GHz and a best case IIP3 of +17.6 dBmwith 6.3 mW power consumption. The LNAs have a broadband input match of 50Ω. The process is 90nm CMOS and with 1.1V supply the LNAs powerconsumption varies between 6.3 mW and 2.3 mW for the best and the worst caseIIP3, respectively.

  • 14.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, p. 79-90Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

  • 15.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Konopacki, J
    Silesian university of technology Gliwice, Poland.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    RF-sampling mixer for zero-IF receiver with high image-rejection.2005In: Swedish System-on-Chip Conference,2005, 2005Conference paper (Other academic)
  • 16.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Konopacki, J.
    Silesian University of Technology, Poland.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    RF-sampling mixer for zero-IF receiver with high image-rejection.2005In: MIXDES 2005,2005, 2005, p. 185-188Conference paper (Refereed)
  • 17.
    Andersson, Stefan
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Konopacki, Jacek
    Institute of Electronics, Silesian University of Technology, Gliwice, Poland.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Noise Analysis and Noise Estimation of an RF-Sampling Front-End using an SC Decimation Filter2006In: Proceedings of the MIXDES 2006 Conference, Gdynia, Poland, 2006, p. 343-348Conference paper (Refereed)
  • 18.
    Andersson, Stefan
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Konopacki, Jacek
    Institute of Electronics, Silesian University of Technology, Gliwice, Poland.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    SC Filter for RF Down Conversion with Wideband Image Rejection2006In: Proceedings of the ISCAS 2006 conference, Kos, Greece, 2006, p. 3542-3545Conference paper (Refereed)
  • 19.
    Andersson, Stefan
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Konopacki, Jacek
    Institute of Electronics, Silesian University of Technology, Gliwice, Poland.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    SC Filter for RF Sampling and Downconversion with Wideband Image Rejection2006In: Journal of Analog Integrated Circuits and Signal Processing by Springer, special issue: MIXDES, ISSN 0925-1030, Vol. 49, no 2, p. 115-122Article in journal (Refereed)
    Abstract [en]

    In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.

  • 20.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Rashad, Ramzan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Direct RF sampling receiver front-end for WLAN.2006In: Swedis system-on-chip conference,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 21.
    Andersson, Stefan
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Rashad, Ramzan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Flexible direct RF-sampling receiver front-end in 0.13 um CMOS.2007In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper (Refereed)
    Abstract [en]

      

  • 22.
    Andersson, Stefan
    et al.
    Ericsson AB, Lund .
    Rashad, Ramzan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Multiband direct RF-sampling receiver font-end for WLAN in 0.13 um CMOS.2007In: European Conference on Circuit Theory and Design, ECCTD,2007, Sevilla, Spain: Oscar Guerra, Universidad de Sevilla , 2007, p. 168-Conference paper (Refereed)
  • 23.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A/D and D/A data conversion for wireless communications transceivers2011In: Digital Front-End in Wireless Communications and Broadcasting: circuits and signal processing / [ed] Fa-Long Luo, Cambridge University Press, 2011, p. 380-412Chapter in book (Other academic)
    Abstract [en]

    Covering everything from signal processing algorithms to integrated circuit design, this complete guide to digital front-end is invaluable for professional engineers and researchers in the fields of signal processing, wireless communication and circuit design. Showing how theory is translated into practical technology, it covers all the relevant standards and gives readers the ideal design methodology to manage a rapidly increasing range of applications. Step-by-step information for designing practical systems is provided, with a systematic presentation of theory, principles, algorithms, standards and implementation. Design trade-offs are also included, as are practical implementation examples from real-world systems. A broad range of topics is covered, including digital pre-distortion (DPD), digital up-conversion (DUC), digital down-conversion (DDC) and DC-offset calibration. Other important areas discussed are peak-to-average power ratio (PAPR) reduction, crest factor reduction (CFR), pulse-shaping, image rejection, digital mixing, delay/gain/imbalance compensation, error correction, noise-shaping, numerical controlled oscillator (NCO) and various diversity methods.

  • 24.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    BiST model for IC RF-transceiver front-end.2003In: IEEE Int. Symposium on Defect and Fault Tolerance in VLSI systems.,2003, Piscataway: IEEE Computer Society , 2003, p. 295-Conference paper (Refereed)
  • 25.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    DfT and BiST Techniques for RF Integrated Circuits.2007Other (Other (popular science, discussion, etc.))
  • 26.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Efficient post-layout timing verification via RLC trees and explicit PWL timing integration.2002In: ICECS 2002,2002, 2002, p. 689-Conference paper (Refereed)
  • 27.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fast BER Test for Digital RF Transceivers2009In: 14th IEEE European Test Symposium, Sevilla, Spain, May 25-29, 2009Conference paper (Refereed)
    Abstract [en]

    The paper presents a fast bit-error-rate (BER) test suitable for digital receivers or transceivers. The test technique makes use of an elevated BER which can be achieved by geometrical translation of the signal constellation points on the IQ plane. As the elevated BER requires much less bits (or symbols) to be measured, significant savings in the test time can be anticipated. Also a maximum sensitivity to impairments in the noise factor is obtained in this way. To develop an effective elevated-BER test for a device in mass production a careful characterization procedure must be carried out, followed by a fine tuning procedure aimed at improving the test resolution and thereby the test coverage. The technique is supported by a simple statistical model and illustrated by a simulation example of a 4QAM receiver.

  • 28.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Fault Modeling of RF blocks based on noise analysis.2004In: 2004 IEEE ISCAS,2004, Piscataway: IEEE Corp. , 2004, p. 513-Conference paper (Refereed)
  • 29.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Loopback BiST for RF front-ends in digital transceivers.2003In: International Symposium on System-on-Chip,2003, Piscataway: Institute of Electrical and Electronic Engineers , 2003, p. 143-Conference paper (Refereed)
  • 30.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    On-chip test for RF IC transceivers2010In: European Microwave Week Workshop, 2010, p. 16-30Conference paper (Refereed)
    Abstract [en]

    Over the years, production test of digital ICs has reached a significant degree of maturity. This progress has been enabled by several techniques, such as fault simulation, test-pattern generation and the built-in-self-test (BiST). Unlike this, much less success has been achieved in the analog/RF and mixed-signal ICs domain, where functional testing has been widely used and the major advances have been in the capabilities of expensive automatic test equipment (ATE). At present, the advancing complexity and performance of mixed-signal and RF ICs are pushing functional test methods and the ATE to the edge of their limits. In this context, alternative approaches based on analog fault modeling, design for testability (DfT), and BiST, so far not appreciated by industry, can largely alleviate the problem and cut the test costs.In this tutorial the essentials of the on-chip test for IC RF transceivers will be presented. The available on chip baseband DSP can serve as a tester while the RF front-end is reconfigured for test. The basic test setup is a loopback, enabled by a test attenuator and in some cases by an offset mixer, too. Different variants of this setup adopt the bypassing technique to boost testability. Also the observability blocks (RF detectors) can be incorporated. The existing limitations and tradeoffs in terms of test feasibility, controllability and observability versus the chip performance will be discussed. The fault-oriented approach and the sensitization techniques will be emphasized. Implementation examples in CMOS technology will be included as well.

  • 31.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    RF on-chip test by reconfiguration technique.2006In: WSEAS International Conference.,2006, 2006Conference paper (Refereed)
    Abstract [en]

      

  • 32.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Andersson, Stefan
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Konopacki, J.
    Silesian University of Technology, Gliwice, Poland.
    SC Filter Design for RF Applications2006In: Mixed design of integrated circuits and systems MIXDES 2006,2006, Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz, Poland , 2006, p. 341-Conference paper (Refereed)
  • 33.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Gonzales, Javier
    EK, ISY, LiU.
    Mixed loopback BiST for RF digital transceivers.2004In: DFT ´04,2004, Piscataway: IEEE, Corp. , 2004, p. 220-Conference paper (Refereed)
  • 34.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Gonzalez Bayon, Javier
    Techniques for Sensitizing RF Path under SER Test.2005In: ISCAS,2005, Galena, Il, USA: Gerard Enteprises, LLC , 2005, p. 4843-Conference paper (Refereed)
  • 35.
    Dabrowski, Jerzy
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Li, Lin
    EK, ISY, LiU.
    Signal path sensitization for built-in-self-test in integrated RF transceivers.2004In: DDECS,2004, Bratislava: Institute of Informatics, SAS , 2004, p. 59-Conference paper (Refereed)
  • 36.
    Dabrowski, Jerzy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Boosting SER Test for RF Transceivers by Simple DSP Technique2007In: DATE '07 Design, Automation & Test in Europe Conference & Exhibition, 2007., IEEE , 2007, p. 1-6Conference paper (Refereed)
    Abstract [en]

    The paper presents a new technique of symbol error rate test (SER) for RF transceivers. A simple DSP algorithm implemented at the receiver baseband is introduced in terms of constellation correction, which is usually used to compensate for IQ imbalance. The test is oriented at detection of impairments in gain and noise figure in a transceiver frontend. The proposed approach is shown to enhance the sensitivity of a traditional SER test to the limits of its counterpart, the error vector magnitude (EVM) test. Its advantage over EVM is in simple implementation, lower DSP overhead and the ability of achieving a larger dynamic range of the test response. Also the test time is saved compared to a traditional SER test. The technique is validated by a simulation model of a Wi-Fi transceiver implemented in MatlabTM.

  • 37.
    Dabrowski, Jerzy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Built-in Loopback Test for IC RF Transceivers2010In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, no 6, p. 933-946Article in journal (Refereed)
    Abstract [en]

    The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

  • 38.
    Dabrowski, Jerzy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Rashad, Ramzan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Offset Loopback Test For IC RF Transceivers2006In: Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz , 2006, p. 583-586Conference paper (Refereed)
    Abstract [en]

    In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade

  • 39.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of Low Noise  Transconductance Amplifier for Current-Mode Wideband RF Frontend2011In: Swedish System-on-Chip Conference (SSOCC), Varberg, Sweden: IEEE Solid-State Circuits Society, 2011Conference paper (Other academic)
  • 40.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low Noise Transconductance  Amplifier Design for Continuous-Time Delta Sigma Wideband Frontend2011In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, p. 825-828Conference paper (Refereed)
    Abstract [en]

    A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 - 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 <; -14 dB while the total power consumption is 3.9 mW for 1.2 V supply.

  • 41.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Qazi, Fahad
    Catena AB, Stockholm, Sweden .
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Analysis and design of low noise transconductance amplifier for selective receiver front-end2015In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, p. 361-372Article in journal (Refereed)
    Abstract [en]

    Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

  • 42.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design and Analysis of High Speed Capacitive Pipeline DACs2014In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, p. 359-374Article in journal (Refereed)
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

  • 43.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Highly linear open-loop output driver design for high speed capacitive DACs2013In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.

  • 44.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, Faculty of Science & Engineering.
    Dabrowski, Jerzy J.
    Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
    Focused Calibration for Advanced RF Test with Embedded RF Detectors2013In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

  • 45.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wideband RF Detector Design for High Performance On-Chip Test2012In: NORCHIP 2012, IEEE , 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.

  • 46.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Qazi, Fahad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design of OTAs for Ultra-Low-Power Sigma-Delta ADCs in Medical Applications2010In: Swedish System-on-Chip Conference (SSoCC), 2010Conference paper (Other academic)
    Abstract [en]

    High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (ΣA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of ΣA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

  • 47.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Qazi, Fahad
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices.
    Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications2010In: International Conference on Signals and Electronic Systems, IEEE , 2010, p. 229-232Conference paper (Refereed)
    Abstract [en]

    High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (ΣA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of ΣA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

  • 48.
    Folkesson, Kalle
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Jakonis, Darius
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Design of RF-sampling receiver front-end.2004In: MIXDES 2004,2004, Lodz, Poland: Technical University of Lodz , 2004, p. 538-Conference paper (Refereed)
  • 49.
    Jakonis, Darius
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Noise analysis of downcenversion sampling mixer2003In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), 2003, p. 181-184Conference paper (Refereed)
    Abstract [en]

    In this paper we address noise properties of an RF downconversion sampling mixer. The relevant noise mechanisms in a SIH circuit are reviewed and investigated. The jitter-induced noise that originates from the sampling clock and the switch driver is shown to be critical in the RF front-end application. Some practical design ideas aimed at optimization of the circuit parameters and the sampling frequency are included. The noise analysis is verified experimentally with a CMOS test chip intended for RF signals up to 2 GHz. The circuit structure and the relevant measurement setup are presented. The obtained results validate our noise analysis.

  • 50.
    Jakonis, Darius
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Dabrowski, Jerzy
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Noise reduction by sampling frequency choice in subsampling mixer.2003In: Swedish system-on-chip conference 2003.,2003, Lund: Lunds universitet , 2003Conference paper (Other academic)
12 1 - 50 of 87
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