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  • 1.
    Azam, Sher
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Jonsson, Rolf
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    High Power, Single Stage SiGaN HEMT Class E Power Amplifier at GHz Frequencies2010In: IEEE International Bhurban Conference on Applied Sciences and Technology, IEEE , 2010Conference paper (Refereed)
  • 2.
    Azam, Sher
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Jonsson, Rolf
    Swedish Defense Research Agency (FOI), Box 1165, SE-581 11 Linkoping, Sweden.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    High Power, Single Stage SiGaN HEMT Class EPower Amplifier at GHz FrequenciesManuscript (preprint) (Other academic)
    Abstract [en]

    A high power single stage class E power amplifier is implemented with lumped elements at 0.89-1.02GHz using Silicon GaN High Electron Mobility Transistor as an active device. The maximum drain efficiency (DE) and power added efficiency (PAE) of 67 and 65 % respectively is obtained with a maximum output power of 42.2 dBm (~ 17 W) and amaximum power gain of 15 dB. We obtained good results at all measured frequencies.

  • 3.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    CMOS RF Power Amplifiers for Wireless Communications2011Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions.

    The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies.

    This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals.

    The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology.

    The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated.

    The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals.

    The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion.

    The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB.

    List of papers
    1. A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
    Open this publication in new window or tab >>A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
    2010 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, p. 241-247Article in journal (Refereed) Published
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

    Place, publisher, year, edition, pages
    Springer Science Business Media, 2010
    Keywords
    CMOS, Power amplifier, Transformers, Wireless LAN
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-58661 (URN)10.1007/s10470-009-9427-2 (DOI)000280593900005 ()
    Note
    The original publication is available at www.springerlink.com: Jonas Fritzin and Atila Alvandpour, A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS, 2010, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (64), 3, 241-247. http://dx.doi.org/10.1007/s10470-009-9427-2 Copyright: Springer Science Business Media http://www.springerlink.com/ Available from: 2010-08-22 Created: 2010-08-20 Last updated: 2019-09-05Bibliographically approved
    2. Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
    Open this publication in new window or tab >>Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
    2008 (English)In: European Microwave Week 2008, Conference Proceedings, 27-31 October 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 1207-1210Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.

    Place, publisher, year, edition, pages
    IEEE, 2008
    Keywords
    CMOS integrated circuits, impedance matching, power amplifiers, transformers, transistors, wireless LAN
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-21009 (URN)10.1109/EUMC.2008.4751677 (DOI)978-2-87487-006-4 (ISBN)
    Conference
    The 38th IEEE European Microwave Conference (EuMC), October 28-30, Amsterdam, The Netherlands
    Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2019-09-05Bibliographically approved
    3. Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
    Open this publication in new window or tab >>Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
    2009 (English)In: Proceedings of 9th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Diego, CA, USA, January 19–21, IEEE , 2009, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of two low- voltage differential class-E power amplifiers (PA) for DECT and Bluetooth fabricated in 130 nm CMOS. In order to minimize the on-chip losses and to achieve a high efficiency at low supply voltages, the PAs do not use on-chip output matching networks. At 1.5V supply voltage, the DECT PA delivers +26.4 dBm of output power with a drain efficiency (DE) and power-added efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA delivers +22.7 dBm at IV with a DE and PAE of 48% and 36%, respectively. A continuous long-term test of 100 hours proves the reliability of the design.

    Place, publisher, year, edition, pages
    IEEE, 2009
    Keywords
    Bluetooth, CMOS integrated circuits, cordless telephone systems, differential amplifiers, power amplifiers, reliability
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-21022 (URN)10.1109/SMIC.2009.4770499 (DOI)978-1-4244-3940-9 (ISBN)
    Conference
    IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09, 19-21 January, San Diego, CA, USA
    Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2019-09-05Bibliographically approved
    4. Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
    Open this publication in new window or tab >>Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
    2010 (English)In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, IEEE , 2010, p. 1907-1910Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4–21.5dBm of output power with drain efficiencies and power-added efficiencies of 56–64% and 46–51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V, the output power dropped about 0.7dB.

    Place, publisher, year, edition, pages
    IEEE, 2010
    Keywords
    CMOS, efficiency, power amplifier, reliability testing
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-58725 (URN)10.1109/ISCAS.2010.5537959 (DOI)978-1-4244-5308-5 (ISBN)
    Conference
    IEEE International Symposium on Circuits and Systems (ISCAS), May 30th - June 2nd, Paris, France
    Available from: 2010-08-24 Created: 2010-08-24 Last updated: 2019-09-05Bibliographically approved
    5. Wideband Fully Integrated +30dBm Class-D Outphasing RF PA in 65nm CMOS
    Open this publication in new window or tab >>Wideband Fully Integrated +30dBm Class-D Outphasing RF PA in 65nm CMOS
    2011 (English)Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +29.7dBm with 26.6% PAE at 1.95 GHz in a standard 65nm CMOS technology. The PA utilizes two on-chip transformers to combine the outputs of four Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled lowvoltage driver, to allow a 5.5V supply without excessive device voltage stress. The measured 3 dB bandwidth was 1.6 GHz (1.2-2.8 GHz). The PA was continuously operated for 168 hours (1 week) without any performance degradation. To evaluate the linearity of the outphasing PA, a WCDMA and an LTE signal (20 MHz, 16-QAM) were used. At +26.0dBm channel power for the WCDMA signal, the measured ACLR at 5MHz and 10MHz offset were -35.6 dBc and -48.4 dBc, respectively. At +22.9dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was -35.9 dBc.

    Keywords
    Outphasing, CMOS, power amplifier
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-71857 (URN)10.1109/ISICir.2011.6131871 (DOI)978-1-61284-863-1 (ISBN)
    Conference
    IEEE International Symposium on Integrated Circuits (ISIC), Singapore, December 12-14
    Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
    6. A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE
    Open this publication in new window or tab >>A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE
    2011 (English)In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE , 2011, p. 127-130Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.

    Place, publisher, year, edition, pages
    IEEE, 2011
    Series
    European Solid-State Circuits Conference, ISSN 1930-8833 ; 2011
    Keywords
    Outphasing, CMOS, power amplifier
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-71858 (URN)10.1109/ESSCIRC.2011.6044881 (DOI)978-1-4577-0702-5 (ISBN)978-1-4577-0703-2 (ISBN)
    Conference
    ESSCIRC
    Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
    7. A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS
    Open this publication in new window or tab >>A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS
    2010 (English)In: Proceedings of the ESSCIRC, 2010, Seville: IEEE , 2010, p. 310-313Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3rd harmonic and reduces the 5th harmonic. The technique creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2nd to 4th harmonics are measured to be -37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.

    Place, publisher, year, edition, pages
    Seville: IEEE, 2010
    Series
    ESSCIRC, ISSN 1930-8833 ; 2010
    Keywords
    CMOS integrated circuits, code division multiple access, harmonic distortion, invertors, linearisation techniques, phase shift keying, power amplifiers, radiofrequency amplifiers, short-circuit currents
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-65459 (URN)10.1109/ESSCIRC.2010.5619706 (DOI)978-1-4244-6662-7 (ISBN)
    Conference
    36th European Solid State Circuits Conference (ESSCIRC), 14-16 September, Seville, Spain
    Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2019-09-05Bibliographically approved
    8. Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
    Open this publication in new window or tab >>Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
    Show others...
    2011 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 642-646Article in journal (Refereed) Published
    Abstract [en]

    This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.

    Keywords
    Amplifier, Complementary metal-oxide-semiconductor (CMOS), Linearization, Outphasing
    National Category
    Control Engineering
    Identifiers
    urn:nbn:se:liu:diva-71781 (URN)10.1109/TCSII.2011.2164149 (DOI)000296009700006 ()
    Funder
    Swedish Foundation for Strategic Research Swedish Research CouncileLLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications
    Available from: 2011-11-04 Created: 2011-11-04 Last updated: 2019-09-05Bibliographically approved
    9. Design and Analysis of a Class-D Stage with Harmonic Suppression
    Open this publication in new window or tab >>Design and Analysis of a Class-D Stage with Harmonic Suppression
    2012 (English)In: Transactions on Circuits and Systems–I: Regular Papers, ISSN 1549-8328, Vol. 59, no 6, p. 1178-1186Article in journal (Refereed) Published
    Abstract [en]

    This paper presents the design and analysis of a low-power Class-D stage in 90nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverterbased output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900MHz, the measured output power was +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% at 1.2V. The 3rd and 5th harmonics were suppressed by 34dB and 4dB, respectively, compared to an inverter-based Class-D stage.1

    Place, publisher, year, edition, pages
    IEEE, 2012
    Keywords
    Radio transmitter, CMOS, harmonic rejection
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-71859 (URN)10.1109/TCSI.2011.2173389 (DOI)000304825700004 ()
    Conference
    EEE Transactions on Circuits and Systems–I: Regular Papers
    Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
    10. Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers
    Open this publication in new window or tab >>Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers
    2011 (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    This paper presents a direct model structure for describing class-D outphasing amplifiers and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals’ phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch.

    Model and predistortion performance are evaluated on a 32 dBm peak output power, class-D outphasing amplifier in CMOS with on-chip transformers. The excitation signal is a 5 MHz wide downlinkWCDMA signal with peak-to-average power ratio (PAPR) of 9.5 dB. Using the proposed digital predistorter the 5 MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 dBc to -45.6 dBc. The 10 MHz ACLR was improved by 6.4 dB, from -44.3 dBc to -50.7 dBc, making the amplifier pass the ACLR requirements.

    Keywords
    Power amplifiers, behavioral modeling, digital predistortion, outphasing amplifier, LINC
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-71860 (URN)
    Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
    11. Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS
    Open this publication in new window or tab >>Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS
    2013 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 7, p. 1915-1928Article in journal (Refereed) Published
    Abstract [en]

    This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

    Keywords
    Outphasing, amplifier, linearization, predistortion, complementary metal-oxide-semiconductor (CMOS)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-71862 (URN)10.1109/TCSI.2012.2230507 (DOI)000322331200020 ()
    Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2019-09-05Bibliographically approved
  • 4.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Power Amplifier Circuits in CMOS Technologies2009Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The wireless market has experienced a remarkable development and growth since the introduction of the first mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, a prime goal of the IC manufacturers is to provide low-cost solutions.

    The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming significantly harder to meet the stringent requirements on linearity, output power, and power efficiency of PAs at lower supply voltages. This has recently triggered extensive studies to investigate the impact of different circuit techniques, design methodologies, and design trade-offs on functionality of PAs in nanometer CMOS technologies.

    This thesis addresses the potential of integrating linear and highly efficient PAs and PA architectures in nanometer CMOS technologies at GHz frequencies. In total four PAs have been designed, two linear PAs and two switched PAs. Two PAs have been designed in a 65nm CMOS technology, targeting the 802.11n WLAN standard operating in the 2.4-2.5GHz frequency band with stringent requirements on linearity. The first linear PA is a two-stage amplifier with LC-based input and interstage matching networks, and the second linear PA is a two-stage PA with transformer-based input and interstage matching networks. Both designs were evaluated for a 72.2Mbit/s, 64-QAM 802.11n OFDM signal with a PAPR of 9.1dB. Both PAs fulfilled the toughest EVM requirement of the standard at average output power levels of 9.4dBm and 11.6dBm, respectively. Matching techniques in both PAs are discussed as well.

    Two Class-E PAs have been designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The first PA is intended for DECT, while the second is intended for Bluetooth. At 1.5V supply voltage and 1.85GHz, the DECT PA delivered +26.4dBm of output power with a drain efficiency (DE) and poweradded efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA had an output power of +22.7dBm at 1.0V with a DE and PAE of 48% and 36%, respectively, at 2.45GHz. The Class-E amplifier stage is also suitable for employment in different linearization techniques like Polar Modulation and Outphasing, where a highly efficient Class-E PA is crucial for a successful implementation.

    List of papers
    1. A 72.2Mbit/s LC-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN
    Open this publication in new window or tab >>A 72.2Mbit/s LC-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN
    2008 (English)In: Proceedings of the 15th Mixed Design of Integrated Circuits and Systems (MIXDES) Conference, IEEE , 2008, p. 155-158Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the design and evaluation of a power amplifier (PA) for WLAN 802.11n in 65nm CMOS technology. The PA utilizes 3.3V thick-gate oxide (5.2nm) transistors and a two-stage differential configuration with two integrated inductors for input and interstage matching. For a 72.2Mbit/s, 64-QAM 802.11n OFDM signal at an average and peak output power of 9.4dBm and 17.4dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 14dBm.

    Place, publisher, year, edition, pages
    IEEE, 2008
    Keywords
    Baluns, CMOS analog integrated circuits, Impedance matching, Power amplifiers, Transformers
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-21025 (URN)978-83-922632-7-2 (ISBN)
    Conference
    15th IEEE Mixed Design of Integrated Circuits and Systems (MIXDES) Conference, June 19-21, Poznan, Poland
    Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2019-09-05Bibliographically approved
    2. A 72.2Mbit/s Transformer-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN
    Open this publication in new window or tab >>A 72.2Mbit/s Transformer-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN
    2008 (English)In: Proceedings of 26th IEEE NORCHIP Conference, IEEE , 2008, p. 54-56Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick-gate oxide (5.2 nm) transistors and a two-stage differential configuration with two integrated transformers for input and interstage matching. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 dBm and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

    Place, publisher, year, edition, pages
    IEEE, 2008
    Keywords
    CMOS analogue integrated circuits, OFDM modulation, UHF power amplifiers, power transformers, quadrature amplitude modulation, wireless LAN
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-21005 (URN)10.1109/NORCHP.2008.4738281 (DOI)978-1-4244-2492-4 (ISBN)
    Conference
    26th IEEE NORCHIP Conference, November 17–18, Tallinn, Estonia
    Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2019-09-05Bibliographically approved
    3. Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
    Open this publication in new window or tab >>Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
    2008 (English)In: European Microwave Week 2008, Conference Proceedings, 27-31 October 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 1207-1210Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.

    Place, publisher, year, edition, pages
    IEEE, 2008
    Keywords
    CMOS integrated circuits, impedance matching, power amplifiers, transformers, transistors, wireless LAN
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-21009 (URN)10.1109/EUMC.2008.4751677 (DOI)978-2-87487-006-4 (ISBN)
    Conference
    The 38th IEEE European Microwave Conference (EuMC), October 28-30, Amsterdam, The Netherlands
    Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2019-09-05Bibliographically approved
    4. Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
    Open this publication in new window or tab >>Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
    2009 (English)In: Proceedings of 9th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Diego, CA, USA, January 19–21, IEEE , 2009, p. 1-4Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents the design of two low- voltage differential class-E power amplifiers (PA) for DECT and Bluetooth fabricated in 130 nm CMOS. In order to minimize the on-chip losses and to achieve a high efficiency at low supply voltages, the PAs do not use on-chip output matching networks. At 1.5V supply voltage, the DECT PA delivers +26.4 dBm of output power with a drain efficiency (DE) and power-added efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA delivers +22.7 dBm at IV with a DE and PAE of 48% and 36%, respectively. A continuous long-term test of 100 hours proves the reliability of the design.

    Place, publisher, year, edition, pages
    IEEE, 2009
    Keywords
    Bluetooth, CMOS integrated circuits, cordless telephone systems, differential amplifiers, power amplifiers, reliability
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-21022 (URN)10.1109/SMIC.2009.4770499 (DOI)978-1-4244-3940-9 (ISBN)
    Conference
    IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09, 19-21 January, San Diego, CA, USA
    Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2019-09-05Bibliographically approved
  • 5.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, p. 241-247Article in journal (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

  • 6.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 72.2Mbit/s Transformer-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN2008In: Proceedings of 26th IEEE NORCHIP Conference, IEEE , 2008, p. 54-56Conference paper (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick-gate oxide (5.2 nm) transistors and a two-stage differential configuration with two integrated transformers for input and interstage matching. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 dBm and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

  • 7.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS2009In: Proceedings of 9th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Diego, CA, USA, January 19–21, IEEE , 2009, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of two low- voltage differential class-E power amplifiers (PA) for DECT and Bluetooth fabricated in 130 nm CMOS. In order to minimize the on-chip losses and to achieve a high efficiency at low supply voltages, the PAs do not use on-chip output matching networks. At 1.5V supply voltage, the DECT PA delivers +26.4 dBm of output power with a drain efficiency (DE) and power-added efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA delivers +22.7 dBm at IV with a DE and PAE of 48% and 36%, respectively. A continuous long-term test of 100 hours proves the reliability of the design.

  • 8.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Voltage High-Efficiency Class-E Power Amplifiers in 130nm CMOS for Short-Range Wireless Communications2009In: in Swedish System on Chip Conference, SSoCC, Arild, May 4-5, Lunds universitet, 2009Conference paper (Other academic)
    Abstract [en]

    This paper presents the design of two lowvoltagedifferential class-E power amplifiers (PA) for DECTand Bluetooth fabricated in 130nm CMOS. In order tominimize the on-chip losses and to achieve a high efficiency atlow supply voltages, the PAs do not use on-chip outputmatching networks. At 1.5V supply voltage, the DECT PAdelivers +26.4dBm of output power with a drain efficiency(DE) and power-added efficiency (PAE) of 41% and 30%,respectively. The Bluetooth PA delivers +22.7dBm at 1V witha DE and PAE of 48% and 36%, respectively. A continuouslong-term test of 100 hours proves the reliability of thedesign.

  • 9.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Ted
    Infineon Technologies Nordic AB Isafjordsgatan 16, SE-164 81 Stockholm, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 72.2Mbit/s LC-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN2008In: Proceedings of the 15th Mixed Design of Integrated Circuits and Systems (MIXDES) Conference, IEEE , 2008, p. 155-158Conference paper (Refereed)
    Abstract [en]

    This paper describes the design and evaluation of a power amplifier (PA) for WLAN 802.11n in 65nm CMOS technology. The PA utilizes 3.3V thick-gate oxide (5.2nm) transistors and a two-stage differential configuration with two integrated inductors for input and interstage matching. For a 72.2Mbit/s, 64-QAM 802.11n OFDM signal at an average and peak output power of 9.4dBm and 17.4dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 14dBm.

  • 10.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Ted
    Infineon Technologies Nordic AB Isafjordsgatan 16, SE-164 81 Kista, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN2008In: European Microwave Week 2008, Conference Proceedings, 27-31 October 2008, Amsterdam, The Netherlands, IEEE , 2008, p. 1207-1210Conference paper (Refereed)
    Abstract [en]

    This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.

  • 11.
    Fritzin, Jonas
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Johansson, Ted
    Infineon Technologies Nordic AB Kista.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Power amplifiers for WLAN in 65nm CMOS2008Conference paper (Other academic)
    Abstract [en]

    This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. EVM, output power levels, and spectral masks are obtained for a 72.2Mbit/s, 64-QAM 802.11n OFDM signal.

  • 12.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jung, Ylva
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Landin, Per Niklas
    Royal Institute of Technology, Sweden.
    Handel, Peter
    Royal Institute of Technology, Sweden.
    Enqvist, Martin
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS2011In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, p. 642-646Article in journal (Refereed)
    Abstract [en]

    This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.

  • 13.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation2012In: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), Lida Ray Technologies Inc., , 2012, p. 45-48Conference paper (Refereed)
    Abstract [en]

    This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.

  • 14.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation2012Conference paper (Refereed)
  • 15.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sundström, Timmy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Ted
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS2010In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, IEEE , 2010, p. 1907-1910Conference paper (Refereed)
    Abstract [en]

    This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4–21.5dBm of output power with drain efficiencies and power-added efficiencies of 56–64% and 46–51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V, the output power dropped about 0.7dB.

  • 16.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE2011In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE , 2011, p. 127-130Conference paper (Refereed)
    Abstract [en]

    This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.

  • 17.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS2010In: Proceedings of the ESSCIRC, 2010, Seville: IEEE , 2010, p. 310-313Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3rd harmonic and reduces the 5th harmonic. The technique creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2nd to 4th harmonics are measured to be -37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.

  • 18.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Fully Integrated High Power CMOS Power Amplifier2011In: Swedish System-on-Chip Conference (SSoCC), IEEE Solid-State Circuits Society, 2011Conference paper (Other academic)
  • 19.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS2012In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 59, no 11, p. 726-730Article in journal (Refereed)
    Abstract [en]

    This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and +29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.

  • 20.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design and Analysis of a Class-D Stage with Harmonic Suppression2012In: Transactions on Circuits and Systems–I: Regular Papers, ISSN 1549-8328, Vol. 59, no 6, p. 1178-1186Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and analysis of a low-power Class-D stage in 90nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverterbased output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900MHz, the measured output power was +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% at 1.2V. The 3rd and 5th harmonics were suppressed by 34dB and 4dB, respectively, compared to an inverter-based Class-D stage.1

  • 21.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Digital Linear CMOS RF Amplifier2010In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
  • 22.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers2011Manuscript (preprint) (Other academic)
    Abstract [en]

    This paper presents a direct model structure for describing class-D outphasing amplifiers and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals’ phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch.

    Model and predistortion performance are evaluated on a 32 dBm peak output power, class-D outphasing amplifier in CMOS with on-chip transformers. The excitation signal is a 5 MHz wide downlinkWCDMA signal with peak-to-average power ratio (PAPR) of 9.5 dB. Using the proposed digital predistorter the 5 MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 dBc to -45.6 dBc. The 10 MHz ACLR was improved by 6.4 dB, from -44.3 dBc to -50.7 dBc, making the amplifier pass the ACLR requirements.

  • 23.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wideband Fully Integrated +30dBm Class-D Outphasing RF PA in 65nm CMOS2011Conference paper (Other academic)
    Abstract [en]

    This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +29.7dBm with 26.6% PAE at 1.95 GHz in a standard 65nm CMOS technology. The PA utilizes two on-chip transformers to combine the outputs of four Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled lowvoltage driver, to allow a 5.5V supply without excessive device voltage stress. The measured 3 dB bandwidth was 1.6 GHz (1.2-2.8 GHz). The PA was continuously operated for 168 hours (1 week) without any performance degradation. To evaluate the linearity of the outphasing PA, a WCDMA and an LTE signal (20 MHz, 16-QAM) were used. At +26.0dBm channel power for the WCDMA signal, the measured ACLR at 5MHz and 10MHz offset were -35.6 dBc and -48.4 dBc, respectively. At +22.9dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was -35.9 dBc.

  • 24.
    Johansson, Ted
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Review of Watt-Level CMOS RF Power Amplifiers2014In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 62, no 1, p. 111-124Article, review/survey (Refereed)
    Abstract [en]

    This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched watt-level PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

  • 25.
    Johansson, Ted
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Solati, Noora
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A high-linearity SiGe RF power amplifier for 3G and 4G small basestations2012In: International journal of electronics (Print), ISSN 0020-7217, E-ISSN 1362-3060, Vol. 99, no 8, p. 1145-1153Article in journal (Refereed)
    Abstract [en]

    This article presents the design and evaluation of a linear 3.3V SiGe power amplifier for 3G and 4G femtocells with 18dBm modulated output power at 2140 MHz. Different biasing schemes to achieve high linearity with low standby current were studied. The adjacent channel power ratio linearity performance with wide-band code division multiple access (3G) and long term evolution (4G) downlink signals were compared and differences analysed and explained.

  • 26.
    Jung, Ylva
    et al.
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, Faculty of Science & Engineering.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Enqvist, Martin
    Linköping University, Department of Electrical Engineering, Automatic Control. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 7, p. 1915-1928Article in journal (Refereed)
    Abstract [en]

    This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

  • 27.
    Khan, H.R.
    et al.
    Electronic Engineering Department, NED University of Engineering and Technology, Karachi, Pakistan.
    Wahab, Q.
    Electronic Engineering Department, NED University of Engineering and Technology, Karachi, Pakistan.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wahab, Qamar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    A 900 MHz 26.8 dBm differential Class-E CMOS power amplifier in German Microwave Conference Digest of Papers, GeMIC 2010, vol , issue , pp 276-2792010In: German Microwave Conference Digest of Papers, GeMIC 2010, 2010, p. 276-279Conference paper (Refereed)
    Abstract [en]

    A 900 MHz differential Class-E amplifier with finite dc inductance has been designed in CMOS. The large inductance of RF choke has been replaced with a finite inductance that provides the required inductive reactance of the class E amplifier. Resonance circuit is realized without series inductor by novel use of lattice LC balun. The amplifier delivers 26.8 dBm power to a 50 O load from a 2.2 V supply. A maximum Power Added Efficiency (PAE) of 43% is achieved.

  • 28.
    Landin, Per N
    et al.
    University of Gavle, Sweden KTH Royal Institute Technology, Belgium Vrije University of Brussel, Belgium .
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Van Moer, Wendy
    University of Gavle, Sweden Vrije University of Brussel, Belgium .
    Isaksson, Magnus
    University of Gavle, Sweden .
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers2012In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 60, no 6, p. 1907-1915Article in journal (Refereed)
    Abstract [en]

    This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths, and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch. less thanbrgreater than less thanbrgreater thanModel and predistortion performance are evaluated on a 32-dBm peak-output-power class-D outphasing PA in CMOS with on-chip transformers. The excitation signal is a 5-MHz downlink WCDMA signal with peak-to-average power ratio of 9.5 dB. Using the proposed digital predistorter, the 5-MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 to -45.6 dBc. The 10-MHz ACLR was improved by 6.4 dB, from -44.3 to -50.7 dBc, making the amplifier pass the 3GPP ACLR requirements.

  • 29.
    Ramazan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Wideband Low Reflection Transmission Lines for Bare Chip on Multilayer PCB2011In: ETRI Journal, ISSN 1225-6463, E-ISSN 2233-7326, Vol. 33, no 3, p. 335-343Article in journal (Refereed)
    Abstract [en]

    The pad pitch of modern RF ICs is in order of few tens of micrometers. Connecting the large number of high speed I/Os to outside world with good signal fidelity and low cost is extremely challenging. To cope with this requirement, we need reflection-free transmission lines from on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow to wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that impedance variation is less then 3Ω for 50Ω microstrip when the width changes from 165μm to 940μm and substrate thickness changes from 100μm to 500μm. The Sparameter measurement on same microstrip shows S11 better then -9dB for the frequency range 1-6GHz.

  • 30.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ahsan, Naveed
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS2009Manuscript (Other academic)
    Abstract [en]

    The software defined radio concept has emerged as a feasible solution for future multigand and multistandard receivers. The proposed software defined radio architecture needs a front-end with moderate or low gain, high linearity, and low noise figure. This paper presents the design and measurement results of low gain RF front-end in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transcjonductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match getter than -8dB up to 8GHz. The front-end achieves voltage conversion gain of 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz at 1GHz. The complete front-end consumers 23mW with active chip area of only 0.048mm2.

  • 31.
    Raza Khan, Hashim
    et al.
    NED University of Engn and Technology, Pakistan .
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ul Wahab, Qamar
    NED University of Engn and Technology, Pakistan .
    A parallel circuit differential class-E power amplifier using series capacitance2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 75, no 1, p. 31-40Article in journal (Refereed)
    Abstract [en]

    Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 mu m CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.

1 - 31 of 31
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