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  • 1.
    Backenius, Erik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On Reduction of Substrate Noise in Mixed-Signal Circuits2005Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.

    In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.

    In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.

  • 2.
    Backenius, Erik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reduction of Substrate Noise in Mixed-Signal Circuits2007Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate.

    Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers.

    The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three.

    Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI.

    An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended.

    A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations.

    List of papers
    1. A strategy for reducing clock noise in mixed-signal circuits
    Open this publication in new window or tab >>A strategy for reducing clock noise in mixed-signal circuits
    2002 (English)In: Proc. IEEE 45th Midwest Symp. on Circuits and Systems, MWSCAS'02, 2002, Vol. 1, p. 29-32Conference paper, Published paper (Refereed)
    Abstract [en]

    Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

    Keywords
    FIR filters, RC circuits, active filters, clocks, flip-flops, integrated circuit noise, mixed analog-digital integrated circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14442 (URN)0-7803-7523-8 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    2. Design of circuits for a robust clocking scheme
    Open this publication in new window or tab >>Design of circuits for a robust clocking scheme
    2004 (English)In: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, p. 185-188Conference paper, Published paper (Refereed)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

    Keywords
    buffer circuits, circuit noise, circuit simulation, clocks, digital integrated circuits, flip-flops, integrated circuit modelling, low-power electronics
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14443 (URN)10.1109/MELCON.2004.1346804 (DOI)0-7803-8271-4 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-05
    3. Evaluation of a clocking strategy with relaxed constraints on clock edges
    Open this publication in new window or tab >>Evaluation of a clocking strategy with relaxed constraints on clock edges
    2004 (English)In: Proc. TENCON'04, 2004, Vol. 4, p. 411-414Conference paper, Published paper (Refereed)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

    Keywords
    CMOS logic circuits, FIR filters, clocks, delays, flip-flops
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14444 (URN)10.1109/TENCON.2004.1414957 (DOI)0-7803-8560-8 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-05
    4. Reduction of simultaneous switching noise in digital circuits
    Open this publication in new window or tab >>Reduction of simultaneous switching noise in digital circuits
    2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 187-190Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.

    Keywords
    CMOS integrated circuits, buffer circuits, clocks, flip-flops, integrated circuit noise, integrated circuit testing
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14445 (URN)10.1109/NORCHP.2006.329207 (DOI)1-4244-0772-9 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    5. Effect of simultaneous switching noise on an analog filter
    Open this publication in new window or tab >>Effect of simultaneous switching noise on an analog filter
    2006 (English)In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, p. 898-901Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

    Keywords
    clocks, digital filters, integrated circuit noise, mixed analog-digital integrated circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14446 (URN)10.1109/ICECS.2006.379934 (DOI)1-4244-0395-2 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    6. Introduction to substrate noise in SOI CMOS integrated circuits
    Open this publication in new window or tab >>Introduction to substrate noise in SOI CMOS integrated circuits
    2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper, Published paper (Other academic)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14447 (URN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    7. Programmable reference generator for on-chip measurement
    Open this publication in new window or tab >>Programmable reference generator for on-chip measurement
    2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

    Keywords
    comparators, digital-analog conversion, electric noise measurement, integrated circuit measurement, integrated circuit noise, programmable circuits, reference circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14448 (URN)10.1109/NORCHP.2006.329251 (DOI)1-4244-0772-9 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    8. Reduction of simultaneous switching noise in analog signal band
    Open this publication in new window or tab >>Reduction of simultaneous switching noise in analog signal band
    2007 (English)In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 148-151Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

    Keywords
    CMOS integrated circuits, adders, flip-flops, frequency-domain analysis, mixed analog-digital integrated circuits, analog signal band, digital clock frequency, frequency components, frequency domain, higher transistor count, pipelined adders, precharged differential cascode switch logic, static CMOS logic, switching noise reduction, transistor level
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14449 (URN)10.1109/ECCTD.2007.4529558 (DOI)978-1-4244-1341-6 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    9. Bidirectional Conversion to Minimum Signed-Digit Representation
    Open this publication in new window or tab >>Bidirectional Conversion to Minimum Signed-Digit Representation
    2006 (English)In: Circuits and Systems, 2006. ISCAS 2006., 2006Conference paper, Published paper (Other academic)
    Abstract [en]

    In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.

    Keywords
    Boolean functions, digital arithmetic, bidirectional conversion, signed-digit representation
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14450 (URN)10.1109/ISCAS.2006.1693109 (DOI)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2015-03-11
  • 3.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Säll, Erik
    Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Ola
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Programmable reference generator for on-chip measurement2006In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper (Refereed)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

  • 4.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Säll, Erik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Bidirectional Conversion to Minimum Signed-Digit Representation2006In: Circuits and Systems, 2006. ISCAS 2006., 2006Conference paper (Other academic)
    Abstract [en]

    In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.

  • 5.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A digital circuit with relaxed clocking2004In: Proc. Swedish System-on-Chip Conf., SSoCC'04, 2004Conference paper (Other academic)
    Abstract [en]

    A clock with adjustable rise and fall time is used in conjunction with a D flip-flop that operates well with this clock. Its intended use is to relax the design of the clock network in digital circuits and to alleviate the problems with simultaneous switching noise in mixed-signal circuits. A test chip has been designed in a 0.35 μm CMOS process. The chip consists of a clock driver with adjustable rise and fall times, and an FIR filter that uses the special D flip-flop in the registers. According to measurements, the digital circuit works well when the rise and fall times of the clock is varied from 0.5 ns to 10 ns. This makes the propagation delay in the critical path to vary between 13.0 ns and 13.7 ns, and the energy dissipation to vary between 1.5 pJ and 1.7 pJ, for an input signal with a transition activity of 0.4.

  • 6.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Characteristics of a differential D flip-flop2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003, Vol. 4Conference paper (Other academic)
    Abstract [en]

    A D flip-flop circuit that works well with long rise and fall times of the clock is characterized. This property is important when we would like to, e.g., relax the constraints on the clock distribution network or reduce the amount of noise generated in a mixed-signal circuit. Since the use of the D flip-flop allows small clock driver circuits, the amount of simultaneous switching noise can be reduced. There is also a potential for power savings with the use of smaller drivers, assuming that the short-circuit current in the flip-flops can be kept low. Moreover, the high frequency content of the clock is reduced, causing the noise that is injected into the substrate to be more easy to suppress. This is important in a mixed-signal circuit where analog circuits are present on the same substrate. The effects of long rise and fall times on the differential D flip-flop used in this work are mainly longer propagation times.

  • 7.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Design of circuits for a robust clocking scheme2004In: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, p. 185-188Conference paper (Refereed)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

  • 8.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Evaluation of a clocking strategy with relaxed constraints on clock edges2004In: Proc. TENCON'04, 2004, Vol. 4, p. 411-414Conference paper (Refereed)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

  • 9.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Introduction to substrate noise in SOI CMOS integrated circuits2005In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper (Other academic)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

  • 10.
    Backenius, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Pin assignment for low simultaneous switching noise2005In: Proc. Swedish System-on-Chip Conf., SSoCC'05, 2005Conference paper (Other academic)
    Abstract [en]

    Simultaneous switching noise (SSN) can degrade the performance of digital circuits. In mixed-signal circuits, the performance of analog circuits are degraded by the SSN that is spread from digital circuits through the substrate to the analog circuits. The most critical parameter when considering SSN is the parasitic inductance in the power supply path from off-chip to on-chip. In this paper, basic theories of inductance of current paths are given for parallel interconnects throughout examples. The results from these examples show that the placement of interconnects plays a big role for the effective inductance. Power supply interconnects should be placed with small distances in between, and so that currents in adjacent interconnects are in opposite directions. With this strategy, a low inductance in the power supply current path can be achieved. The importance of choosing a good package for the silicon die is also briefly discussed.

  • 11.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Reduction of simultaneous switching noise in digital circuits2006In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 187-190Conference paper (Refereed)
    Abstract [en]

    In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.

  • 12.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Hägglund, Robert
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A strategy for reducing clock noise in mixed-signal circuits2002In: Proc. IEEE 45th Midwest Symp. on Circuits and Systems, MWSCAS'02, 2002, Vol. 1, p. 29-32Conference paper (Refereed)
    Abstract [en]

    Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

  • 13.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Hägglund, Robert
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Effect of simultaneous switching noise on an analog filter2006In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, p. 898-901Conference paper (Refereed)
    Abstract [en]

    In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

  • 14.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Hägglund, Robert
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reduction of Clock Noise in Mixed-Signal Circuits2002In: Proc. National Conf. on Radio Science, RVK'02, 2002, Vol. 1, p. 197-201Conference paper (Other academic)
    Abstract [en]

    A major concern in mixed-signal circuits is the noise injected by the digital circuits into sensitive analog circuits. Of particular interest in this work is the problem with large capacitive coupling between the digital clock network and the substrate shared with the analog circuits. It is in general more easy to reduce low frequency noise compared with high frequency noise. Therefore, we have developed a strategy where we reduce the high frequency content of the clock by using smooth clock edges, and a special digital flip-flop circuit. This strategy will be evaluated in a test chip where we can control the rise and fall time of the clock edges of a high-performance digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

  • 15.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Settu, V.B.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Reduction of simultaneous switching noise in analog signal band2007In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 148-151Conference paper (Refereed)
    Abstract [en]

    In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

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