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  • 1.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmailzadeh Najari, Omid
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS2013In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 60, no 7, p. 387-391Article in journal (Refereed)
    Abstract [en]

    This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

  • 2.
    Edman, Anders
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Synchronous Latency-Insensitive Design for Multiple Clock Domain2005In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), IEEE Explore , 2005, p. 83-86Conference paper (Refereed)
    Abstract [en]

    Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.

  • 3.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A low voltage and process variation tolerant SRAM cell in 90-nm CMOS2010In:  International Symposium on VLSI Design Automation and Test, IEEE , 2010, p. 78-81Conference paper (Refereed)
    Abstract [en]

    In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.

  • 4.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation2012In: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), Lida Ray Technologies Inc., , 2012, p. 45-48Conference paper (Refereed)
    Abstract [en]

    This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.

  • 5.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Class-D Stage with Third Harmonic Suppression and DLL-Based Phase Generation2012Conference paper (Refereed)
  • 6.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    1.56 HGz On-chip Resonant Clocking in 130nm CMOS.2006In: IEEE Custom Integrated Circuits Conference CICC,2006, Piscataway: IEEE , 2006, p. 241-Conference paper (Refereed)
  • 7.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS2006In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, p. 464-467Conference paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

  • 8.
    Hansson, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A low-power on-chip resonant clocking technique.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 9.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A CMOS implementation of min-max circuits in current mode and a sample fuzzy application.2004In: IEEE Fuzzy Systems Symposium,2004, Piscataway: IEEE , 2004, p. 941--946Conference paper (Refereed)
  • 10.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Circuit Techniques for On-Chip Clocking and Synchronization2006Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.

    This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-μm CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.

    List of papers
    1. A New Mesochronous Clocking Scheme for Synchronization in SoC
    Open this publication in new window or tab >>A New Mesochronous Clocking Scheme for Synchronization in SoC
    2004 (English)In: Proceedings of the 2004 International Symposium on Circuits and Systems(ISCAS), 2004, Vol. 6, p. 605-608Conference paper, Published paper (Refereed)
    Abstract [en]

    Future System-on-Chips (SoCs) need a new strategy for synchronization and clocking. In large-scale and high-speed systems, the traditional globally synchronous approach is not longer viable, due to severe wire delays. Instead new solutions as "Globally Asynchronous, Locally Synchronous" (GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this paper we present such an approach together with a circuit solution in 0.18 μm CMOS process that allows clocking frequencies up to 5 GHz.

    Series
    , ISSN 1057-7122
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14042 (URN)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05
    2. A Study of Injection Locking in Ring Oscillators
    Open this publication in new window or tab >>A Study of Injection Locking in Ring Oscillators
    2005 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, p. 5465-5468Conference paper, Published paper (Refereed)
    Abstract [en]

    The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

    Keywords
    injection locking, ring oscillators, phase noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14043 (URN)10.1109/ISCAS.2005.1465873 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    3. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, p. 464-467Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

    Keywords
    CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    4. A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
    Open this publication in new window or tab >>A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
    2006 (English)In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, p. 257-260Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

    Keywords
    CMOS
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14045 (URN)10.1109/SOCC.2006.283893 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    5. A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    Open this publication in new window or tab >>A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    2006 (English)In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p. 5143-5146Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

    Keywords
    quadrature VCO, tuning range, coupled ring oscillators, CMOS
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14046 (URN)10.1109/ISCAS.2006.1693790 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
  • 11.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    EMI reduction by resonant clock distribution networks2010In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
  • 12.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power Low-Jitter Clock Generation and Distribution2008Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded.

    The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz.

    In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz.

    List of papers
    1. A Study of Injection Locking in Ring Oscillators
    Open this publication in new window or tab >>A Study of Injection Locking in Ring Oscillators
    2005 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, p. 5465-5468Conference paper, Published paper (Refereed)
    Abstract [en]

    The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

    Keywords
    injection locking, ring oscillators, phase noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14043 (URN)10.1109/ISCAS.2005.1465873 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    2. A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    Open this publication in new window or tab >>A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
    2006 (English)In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p. 5143-5146Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

    Keywords
    quadrature VCO, tuning range, coupled ring oscillators, CMOS
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14046 (URN)10.1109/ISCAS.2006.1693790 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    3. First-Harmonic Injection-Locked Ring Oscillators
    Open this publication in new window or tab >>First-Harmonic Injection-Locked Ring Oscillators
    2006 (English)In: Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), 10-13 September, San José, CA, USA, 2006, p. 733-736Conference paper, Published paper (Other academic)
    Abstract [en]

    This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed

    Keywords
    CMOS integrated circuits, frequency multipliers, harmonic oscillators (circuits), injection locked oscillators, logic circuits
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14893 (URN)10.1109/CICC.2006.320927 (DOI)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
    4. A Study of First-Harmonic Injection Locking for On-chip Applications
    Open this publication in new window or tab >>A Study of First-Harmonic Injection Locking for On-chip Applications
    (English)Manuscript (Other academic)
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14894 (URN)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
    5. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
    2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, p. 464-467Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

    Keywords
    CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
    Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2019-09-05Bibliographically approved
    6. Jitter Characteristic in Charge Recovery Resonant Clock Distribution
    Open this publication in new window or tab >>Jitter Characteristic in Charge Recovery Resonant Clock Distribution
    2007 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, p. 1618-1625 Article in journal (Refereed) Published
    Abstract [en]

    This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

    Keywords
    CMOS digital integrated circuits, clocks, jitter, resonators
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14898 (URN)10.1109/JSSC.2007.896691 (DOI)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
    7. Low-Power Bufferless Resonant Clock Distribution Networks
    Open this publication in new window or tab >>Low-Power Bufferless Resonant Clock Distribution Networks
    2007 (English)In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, p. 960-963Conference paper, Published paper (Refereed)
    Abstract [en]

    The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

    Place, publisher, year, edition, pages
    Montreal: ReSMiQ, 2007
    Keywords
    CMOS integrated circuits, VLSI, clocks, timing jitter
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14900 (URN)10.1109/MWSCAS.2007.4488725 (DOI)
    Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2019-09-05
  • 13.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Simultaneous switching noise reduction by resonant clock distribution networks2014In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 47, no 2, p. 242-249Article in journal (Refereed)
    Abstract [en]

    Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.

  • 14.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS2006In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, p. 257-260Conference paper (Other academic)
    Abstract [en]

    This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

  • 15.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.5-GHz DLL-based multiphase clock generator in 90-nm CMOS.2008In: Swedish System-on-Chip Conference SSoCC.,2008, 2008Conference paper (Other academic)
  • 16.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2-GHz 7-mW Digital DLL-Based Frequency Multiplier in 90-nm CMOS2008In: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, Bristol, UK: IOP Institute of Physics , 2008, p. 86-89Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power low-jitter digital DLL-based frequency multiplier in 90-nm CMOS. In order to reduce the jitter and power consumption due to dithering in the lock condition, digital DLL operates in the open-loop mode after locking. To keep track of any potential phase error introduced by the environmental variations, a compensation mechanism is employed. The proposed frequency multiplier operates at 2-GHz utilizing a 1-V supply. It occupies 0.037 mm2 of active area and dissipates 7-mW power at 2-GHz. The measured peak-to-peak and rms clock jitter at the output of the frequency multiplier are 9.5 ps and 1.6 ps, respectively.   

  • 17.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode2009In: IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN 0018-9200, Vol. 44, no 7, p. 1907-1913Article in journal (Refereed)
    Abstract [en]

    This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.

  • 18.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Study of First-Harmonic Injection Locking for On-chip ApplicationsManuscript (Other academic)
  • 19.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Study of Injection Locking in Ring Oscillators2005In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, p. 5465-5468Conference paper (Refereed)
    Abstract [en]

    The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

  • 20.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators2006In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p. 5143-5146Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

  • 21.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    EMI reduction by resonant clock distribution networks2010In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, IEEE , 2010, p. 977-980Conference paper (Refereed)
    Abstract [en]

    In today's automotive vehicles, electromagnetic interference (EMI) from electronic circuits has become a serious concern. The discussion in this paper proves that a clock signal generated by a resonant clock distribution network exhibits better EMI performance compared to that of a conventional buffer-driven clock network. This discussion is supported by analyzing different clock spectrums and using a simple model of simultaneous switching noise (SSN). According to simulation results presented in a 90-nm CMOS process, using a sinusoidal clock instead of a trapezoidal one, the magnitude of the first tone in the spectrum of SSN is reduced at least by 6.7 dB.

  • 22.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    First-harmonic injection locking in ring oscillators.2006In: Swedish system-on-chip conference.,2006, Lund: Lunds universitet , 2006Conference paper (Refereed)
  • 23.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    First-Harmonic Injection-Locked Ring Oscillators2006In: Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), 10-13 September, San José, CA, USA, 2006, p. 733-736Conference paper (Other academic)
    Abstract [en]

    This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed

  • 24.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Injection-Locked Ring Oscillators.2005In: SSoCC 2005,2005, 2005Conference paper (Other academic)
  • 25.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Esmaeil Zadeh, Iman
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A multi-segment clocking scheme to reduce on-chip EMI2011In: IEEE International SoC Conference (SoCC), Taipei, Taiwan: IEEE , 2011, p. 251-255Conference paper (Refereed)
    Abstract [en]

    This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.

  • 26.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jitter Characteristic in Charge Recovery Resonant Clock Distribution2007In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, p. 1618-1625 Article in journal (Refereed)
    Abstract [en]

    This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

  • 27.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jitter Characteristic in Resonant Clock Distribution2006In: Proceedings of the 32nd ESSCIRC conference 18-22 September 2006, 2006, p. 464-467Conference paper (Refereed)
  • 28.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-Power Bufferless Resonant Clock Distribution Networks2007In: Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Montreal: ReSMiQ , 2007, p. 960-963Conference paper (Refereed)
    Abstract [en]

    The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

  • 29.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Low-power low-jitter bufferless resonant clocking.2007In: Swedish System-on-Chip Conference SSoCC,2007, Göteborg: CTH , 2007Conference paper (Refereed)
  • 30.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Sadeghifar, Mohammad Reza
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Fredriksson, P.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jansson, C.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Niklaus, F.
    FAUN AB.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A low-noise readout circuit in 0.35-μm CMOS for low-cost uncooled FPA infrared network camera2009In: Infrared Technology and Applications XXXV, Proceedings of SPIE - The International Society for Optical Engineering, vol 7298, SPIE - International Society for Optical Engineering, 2009, Vol. 7298, article id 72982FConference paper (Refereed)
    Abstract [en]

    This paper describes a differential readout circuit technique for uncooled Infrared Focal Plane Arrays (IRFPA) sensors. The differential operation allows an efficient rejection of the common-mode noise during the biasing and readout of the detectors. This has been enabled by utilizing a number of blind and thermally-isolated IR bolometers as reference detectors. In addition, a pixel-wise detector calibration capability has been provided in order to allow efficient error corrections using digital signal processing techniques. The readout circuit for a 64×64 test bolometer-array has been designed in a standard 0.35-μm CMOS process. Circuit simulations show that the analog readout at 60 frames/s consumes 30 mW from a 3.3-V supply and results in a noise equivalent temperature difference (NETD) of 125 mK for f/1 infrared optics.

  • 31.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A New Mesochronous Clocking Scheme for Synchronization in SoC2004In: Proceedings of the 2004 International Symposium on Circuits and Systems(ISCAS), 2004, Vol. 6, p. 605-608Conference paper (Refereed)
    Abstract [en]

    Future System-on-Chips (SoCs) need a new strategy for synchronization and clocking. In large-scale and high-speed systems, the traditional globally synchronous approach is not longer viable, due to severe wire delays. Instead new solutions as "Globally Asynchronous, Locally Synchronous" (GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this paper we present such an approach together with a circuit solution in 0.18 μm CMOS process that allows clocking frequencies up to 5 GHz.

  • 32.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Söderquist, Ingemar
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reliability Challenges in Avionics due to Silicon Aging2012In: 2012 IEEE 15TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS and SYSTEMS (DDECS), IEEE , 2012, p. 342-347Conference paper (Refereed)
    Abstract [en]

    Todays aviation systems are strongly dependent on electronics. Avionics (i.e., aviation electronics) should be highly reliable due to the nature of their applications. CMOS technology, which is widely used in the fabrication of integrated circuits, is continuously scaled to achieve higher performance and higher integration density (i.e., the well-known Moores law). This scaling property creates new challenges in reliability of avionics. As an example, the aging process is speeded up resulting in shorter time to wear-out. This paper investigates reliability challenges in design of avionics caused by silicon aging. It is shown that in the circuits and systems designed in modern CMOS technology, aging phenomenon have to be considered as a serious concern.

  • 33.
    Ohlsson, Henrik
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Johansson, Kenny
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System.
    Löwenborg, Per
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 16 GSPS 0.18 µm CMOS decimator for single-bit ∑∆-modulation.2004In: Norchip,2004, Piscataway: IEEE Inc. , 2004, p. 175-Conference paper (Refereed)
  • 34.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB2012In: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), IEEE , 2012, p. 2027-2030Conference paper (Refereed)
    Abstract [en]

    A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.

  • 35.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Low-Power Direct IQ Upconversion Technique Based on Duty-Cycled Multi-Phase Sub-Harmonic Passive Mixers for UWB Transmitters2014Conference paper (Refereed)
    Abstract [en]

    This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO frequency, i.e., a sub-harmonic frequency of the carrier. As a result, several benefits can be gained. Requiring a sub-harmonic LO (SHLO) relaxes the requirements on the frequency synthesizer circuitry. Moreover, the need for digital power-hungry or analog inductor-based high frequency LO buffers is alleviated. In addition, since rail-to-rail LO signals can be provided easier and with less power consumption at lower frequencies, we can employ passive mixers in the mixer array to improve the power consumption and linearity of the overall transmitter. Multi-phase LO clocks required by the proposed scheme are provided using a delay-locked loops (DLL). The proposed architecture is utilized in design of a WiMedia-UWB direct-conversion TX in a standard 65-nm CMOS technology. The MC simulation results indicate LO leakage of –68 dBc and sideband rejection of –39 dBc. The overall system draw 6.8 mA from a 1.2 V supply.

  • 36.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Process Variation Tolerant DLL-Based UWB Frequency Synthesizer2012In: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE , 2012, p. 558-561Conference paper (Refereed)
    Abstract [en]

    A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.

  • 37.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A quadrature UWB frequency synthesizer with dynamic settling-time calibration2013In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE , 2013, p. 2480-2483Conference paper (Refereed)
    Abstract [en]

    This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.

  • 38.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Self-Calibration Technique for Fast-Switching Frequency-Hopped UWB Synthesis2014In: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014,, IEEE , 2014, p. 154-159Conference paper (Refereed)
    Abstract [en]

    This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during a start-up phase. During the normal operation when the hopping command arrives, the stored voltages are applied to the loop in an open-loop regime to perform fast channel switching of sub-9.5 ns which is required by WiMedia-UWB standard. Certain architectural and circuit methods are utilized in order to minimize the error in the sampled voltages caused by channel charge injection and clock feedthrough of the sampling switches. Since the proposed fast-switching scheme does not require a wide loop bandwidth, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples resulting in sideband spurs is eliminated. Moreover, the VCDL can be biased in the low-gain region of its transfer function to reduce its noise transfer to the synthesizer output. The proposed architecture is implemented in a 65-nm standard CMOS process and the simulation results indicate a worst-case band switching time of less than 5.5 ns.

  • 39.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 11, p. 3075-3084Article in journal (Refereed)
    Abstract [en]

    Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.

  • 40.
    Ojani, Amin
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers2015In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 1, p. 273-282Article in journal (Refereed)
    Abstract [en]

    Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

  • 41.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krysander, Mattias
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, The Institute of Technology.
    Klein, Markus
    SAAB AB, Linköping, Sweden.
    Söderquist, Ingemar
    SAAB AB, Linköping, Sweden.
    Crona, Anneli
    SAAB AB, Linköping, Sweden.
    Fransson, Torbjörn
    SAAB AB, Linköping, Sweden.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Prognostics of Electronic Systems through Power Supply Current Trends2008Conference paper (Refereed)
    Abstract [en]

    As today’s avionic systems highly rely on electronic components, the prognostic of electronic systems in the context of avionics has become crucial. This paper presents a prognostic method applicable to electronic components and systems based on the analysis of the power supply current. In this method, the focus is on trends in the measured power supply current of the device under prognostic process. The discussion in this paper reveals that there is a measurable relationship between the supply current and the remaining lifetime of the electronic devices. The presented methodology is supported by circuit simulations performed on a system consisting of reference circuitry. The prognostic method shows great promise due to the ability of being applicable at any prognostic level.

  • 42.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Mesgarzadeh, Behzad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krysander, Mattias
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering.
    Klein, Markus
    Saab AB.
    Söderquist, Ingemar
    Saab AB.
    Krona, Anneli
    Saab AB.
    Fransson, Torbjörn
    Saab AB.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Prognostics of electronic systems through power supply current trends2008In: IEEE Internatioanl Conference on Prognostics and Health Management, Denver, USA, 2008Conference paper (Other academic)
    Abstract [en]

    As today's avionic systems highly rely on electronic components, the prognostic of electronic systems in the context of avionics has become crucial. This paper presents a prognostic method applicable to electronic components and systems based on the analysis of the power supply current. In this method, the focus is on trends in the measured power supply current of the device under prognostic process. The discussion in this paper reveals that there is a measurable relationship between the supply current and the remaining lifetime of the electronic devices. The presented methodology is supported by circuit simulations performed on a system consisting of reference circuitry. The prognostic method shows great promise due to the ability of being applicable at any prognostic level.

1 - 42 of 42
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