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  • 1.
    Carlsson, Jonas
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Contributions to Asynchronous Communication Ports for GALS Systems2006Doktoravhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    Digital systems commonly use a single global clock signal to synchronize the whole system. This is not always possible and it can be more advantageously to divide the system into separate clock domains, where each clock domain can operate with its own clock frequency. Communication between the different clock domains are not trivial and must be handled with care. Several schemes can be used depending on the relation between the clock frequencies of the communicating clock domains. This thesis focuses on the Globally Asynchronous Locally Synchronous (GALS) scheme, in which all communications between clock domains are handled using dedicated communication channels. These communication channels use asynchronous handshaking protocols to transfer information between clock domains. No global clock signal is used and the clock signal is instead local for each clock domain.

    An efficient design flow for GALS system has been developed, which allows a designer to implement GALS systems without prior knowledge of asynchronous circuits. The GALS design flow starts with a high-level model of the system behavior and ends with an implementation in an FPGA or an ASIC. The design flow can also increase the design efficiency for GALS system since the flow alleviates the design and placement of the asynchronous circuits for the designer. A tool that handles the asynchronous circuits in the design flow has been developed.

    Two types of communication ports have been developed to handle the communication between clock domains. Both of these ports can be used in systems with static schedule or dynamic schedule of transactions. One of the communication ports can easily be migrated to a new CMOS process, since it only uses standard-cells that care provided by most vendors of CMOS processes. A clock gating circuit has been developed to allow a clock domain to use an external stable clock signal to create an internal stoppable clock signal. A stoppable local clock is used to eliminate problems with metastability when transferring data between clock domains with arbitrary clock frequencies.

    In order to validate the design flow and proposed circuitry, has an integrated circuit for 2-dimensional Discrete Cosine Transform been implemented using the GALS scheme and one of the proposed communication ports. The circuit has been implemented using a standard-cell library in a 0.35 mm CMOS process. A few possible improvements to the implementation are also discussed in the thesis.

    The GALS design flow with the asynchronous wrapper generation tool has been used to implement the digital baseband processing in the physical layer of the IEEE 802.11a transmitter. The transmitter is built using multiple clock domains. The transmitter has been implemented and tested in a Stratix II FPGA.

  • 2.
    Carlsson, Jonas
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    Studies on asynchronous communication ports for GALS systems2005Licentiatavhandling, monografi (Annet vitenskapelig)
    Abstract [en]

    Digital systems generally use a global clock signal for the whole system. A System-on-Chip may have to communicate with the environment, using several different data rates that does not fit well to the single global clock frequency. When designing a digital system, it might be beneficial to divide the system into different clock domains where each domain can operate with its own clock frequency.

    In this thesis, various clocking schemes are discussed. The synchronous clocking schemes that are discussed are mesochronous, plesiochronous, rational, oversampling and arbitrary clocking schemes.

    The thesis focuses on the Globally Asynchronous Locally Synchronous scheme. This scheme transfers information between the different clock domains through dedicated communication channels. These communication channels use asynchronous handshaking protocols to transfer information without the necessity for a clock.

    A communication channel consists of a transmitting and receiving port. Two types of communication ports are proposed in the thesis. The communication ports can be used either in a system with a static schedule or dynamic schedule of transactions. One of the ports can easily be implemented in different CMOS processes, since it only uses standard cells that can be found in most existing CMOS processes standard library.

    A 2-dimensional Discrete Cosine Transform has been implemented using the GALS scheme and one of the proposed communication ports. The 2-D DCT has been implemented using a standard cell library supplied by AMS fora 0.35 µm CMOS process. A few improvements to the implementation are also discussed in the thesis.

  • 3.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Palmkvist, Kent
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems2006Inngår i: IEEE NORCHIP,2006, 2006Konferansepaper (Fagfellevurdert)
  • 4.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Palmkvist, Kent
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    An 8-by-8 Point 2D DCT Processor Based on the GALS Approach2003Inngår i: IEEE NorChip Conf.,2003, 2003Konferansepaper (Fagfellevurdert)
  • 5.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Palmkvist, Kent
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Design Flow for Globally Asynchronous Locally Synchronous Systems using Conventional Synchronous Design Tools2006Inngår i: WSEAS Transactions on Circuits and Systems, ISSN 1109-2734, Vol. 5, nr 7, s. 953-960Artikkel i tidsskrift (Annet vitenskapelig)
  • 6.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Palmkvist, Kent
    Linköpings universitet, Institutionen för systemteknik.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    GALS Implementation of a 2-D DCT Processor2004Inngår i: Swedish System-on-Chip Conference 2004,2004, 2004Konferansepaper (Annet vitenskapelig)
  • 7.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Palmkvist, Kent
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    GALS port implementation in FPGA2005Inngår i: National Conf. Radio Science RVK,2005, 2005Konferansepaper (Fagfellevurdert)
  • 8.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Palmkvist, Kent
    Linköpings universitet, Institutionen för systemteknik.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Port controller for GALS with first come first served function2004Inngår i: TENCON 2004,2004, 2004Konferansepaper (Annet vitenskapelig)
  • 9.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Institutionen för systemteknik.
    Palmkvist, Kent
    Linköpings universitet, Institutionen för systemteknik.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Port controllers for a GALS Implementation of a 2-D DCT Processor2004Inngår i: 10th International Symposium on Integrated Circuits, Devices and Systems,2004, 2004Konferansepaper (Annet vitenskapelig)
  • 10.
    Carlsson, Jonas
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Palmkvist, Kent
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    Synchronous Design Flow for Globally Asynchronous Locally Synchronous Systems2006Inngår i: WSEAS Int. Conf. Circuits,2006, 2006Konferansepaper (Fagfellevurdert)
  • 11.
    Zhuang, Shengxian
    et al.
    Sch. of Electr. Eng. Southwest Jiaotong Univ..
    Carlsson, Jonas
    Linköpings universitet, Institutionen för systemteknik.
    Li, Weidong
    Linköpings universitet, Institutionen för systemteknik.
    Palmkvist, Kent
    Linköpings universitet, Institutionen för systemteknik.
    Wanhammar, Lars
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för systemteknik, Elektroniksystem.
    GALS based approach to the implementation of the DWT filter bank2004Inngår i: International Conference on Signal Processing,2004, Beijing: Publishing House of Electronics Industry , 2004, s. 567-Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a VLSI implementation method for one-dimensional discrete wavelet transform (1D-DWT) filter bank based on the GALS systems approach. An asynchronous wrapper, which includes two data communication ports and a local clock controller, is designed for the asynchronous data communication between the locally synchronous filtering modules in the wavelet filter bank. The detailed design methodology for the GALS architecture of ID-DWT filter bank is presented, and the circuits are validated with VHDL and implemented with standard CMOS technology.

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